WebSVN RSS feed – pentevoThu, 16 Apr 2026 16:40:26 +0300WebSVN 2.8.5-DEVenhttp://svn.zxevo.ru/log.php?repname=pentevo&path=%2Ffpga%2Ftests%2Ftest_dram%2Ftest_dram.qws&max=20& Sat, 21 Nov 2009 21:06:56 +0300lvd<div><strong>lvd – 195 file(s) modified</strong><br/>initial commit of FPGA files</div>x /file1st<br />+ /fpga<br />+ /fpga/current<br />+ /fpga/current/common<br />+ /fpga/current/common/resetter.v<br />+ /fpga/current/common/spi2.v<br />+ /fpga/current/dram<br />+ /fpga/current/dram/arbiter.png<br />+ /fpga/current/dram/arbiter.v<br />+ /fpga/current/dram/cycles.txt<br />+ /fpga/current/dram/dram.v<br />+ /fpga/current/dram/test_compile.zip<br />+ /fpga/current/include<br />+ /fpga/current/include/tune.v<br />+ /fpga/current/quartus<br />+ /fpga/current/quartus/pentevo_0_01.qpf<br />+ /fpga/current/quartus/pentevo_0_01.qws<br />+ /fpga/current/quartus/top.qsf<br />+ /fpga/current/quartus/top.rbf<br />+ /fpga/current/quartus/top.sof<br />+ /fpga/current/quartus/top_fix_ide_maybe.zip<br />+ /fpga/current/README<br />+ /fpga/current/sim_cdv<br />+ /fpga/current/sim_cdv/a<br />+ /fpga/current/sim_cdv/b<br />+ /fpga/current/sim_cdv/tb.v<br />+ /fpga/current/sim_models<br />+ /fpga/current/sim_models/drammem.v<br />+ /fpga/current/sim_models/ram.v<br />+ /fpga/current/sim_models/rom.v<br />+ /fpga/current/sim_models/T80.vhd<br />+ /fpga/current/sim_models/T80a.vhd<br />+ /fpga/current/sim_models/T80_ALU.vhd<br />+ /fpga/current/sim_models/T80_MCode.vhd<br />+ /fpga/current/sim_models/T80_Pack.vhd<br />+ /fpga/current/sim_models/T80_Reg.vhd<br />+ /fpga/current/slave<br />+ /fpga/current/slave/slavespi.v<br />+ /fpga/current/slave/zx.h<br />+ /fpga/current/slave/zx_keys.txt<br />+ /fpga/current/texts<br />+ /fpga/current/texts/dram_access.txt<br />+ /fpga/current/texts/readme.txt<br />+ /fpga/current/texts/video_modes.txt<br />+ /fpga/current/top.v<br />+ /fpga/current/vg93<br />+ /fpga/current/vg93/vg93.v<br />+ /fpga/current/video<br />+ /fpga/current/video/addresses.txt<br />+ /fpga/current/video/fetch.v<br />+ /fpga/current/video/synch.v<br />+ /fpga/current/video/syncv.v<br />+ /fpga/current/video/videoout.v<br />+ /fpga/current/z80<br />+ /fpga/current/z80/zbus.v<br />+ /fpga/current/z80/zclock.v<br />+ /fpga/current/z80/zint.v<br />+ /fpga/current/z80/zmem.v<br />+ /fpga/current/z80/zports.v<br />+ /fpga/tests<br />+ /fpga/tests/test_dram<br />+ /fpga/tests/test_dram/dram.v<br />+ /fpga/tests/test_dram/dram_control.v<br />+ /fpga/tests/test_dram/main.qsf<br />+ /fpga/tests/test_dram/main.rbf<br />+ /fpga/tests/test_dram/main.sof<br />+ /fpga/tests/test_dram/main.v<br />+ /fpga/tests/test_dram/main_.v<br />+ /fpga/tests/test_dram/mem_tester.v<br />+ /fpga/tests/test_dram/resetter.v<br />+ /fpga/tests/test_dram/rnd_vec_gen.v<br />+ /fpga/tests/test_dram/sram_control.v<br />+ /fpga/tests/test_dram/stable.sof<br />+ /fpga/tests/test_dram/test_dram.qpf<br />+ /fpga/tests/test_dram/test_dram.qws<br />+ /fpga/tests/test_ledblink<br />+ /fpga/tests/test_ledblink/dram.v<br />+ /fpga/tests/test_ledblink/main.qsf<br />+ /fpga/tests/test_ledblink/main.v<br />+ /fpga/tests/test_ledblink/stable.sof<br />+ /fpga/tests/test_ledblink/test_ledblink.qpf<br />+ /fpga/tests/test_ledblink/test_ledblink.qws<br />+ /fpga/_ver0.00<br />+ /fpga/_ver0.00/common<br />+ /fpga/_ver0.00/common/resetter.v<br />+ /fpga/_ver0.00/common/spi2.v<br />+ /fpga/_ver0.00/dram<br />+ /fpga/_ver0.00/dram/arbiter.png<br />+ /fpga/_ver0.00/dram/arbiter.v<br />+ /fpga/_ver0.00/dram/cycles.txt<br />+ /fpga/_ver0.00/dram/dram.v<br />+ /fpga/_ver0.00/dram/test_compile<br />+ /fpga/_ver0.00/dram/test_compile/arbiter.cvwf<br />+ /fpga/_ver0.00/dram/test_compile/arbiter.qsf<br />+ /fpga/_ver0.00/dram/test_compile/arbiter_description.txt<br />+ /fpga/_ver0.00/dram/test_compile/test_compile.qpf<br />+ /fpga/_ver0.00/dram/test_compile/test_compile.qws<br />+ /fpga/_ver0.00/dram/test_compile/test_compile.v<br />+ /fpga/_ver0.00/dram_access.txt<br />+ /fpga/_ver0.00/include<br />+ /fpga/_ver0.00/include/tune.v<br />+ /fpga/_ver0.00/keyboard<br />+ /fpga/_ver0.00/main.v<br />+ /fpga/_ver0.00/readme.txt<br />+ /fpga/_ver0.00/sim_cdv<br />+ /fpga/_ver0.00/sim_cdv/a<br />+ /fpga/_ver0.00/sim_cdv/b<br />+ /fpga/_ver0.00/sim_cdv/sim_cdv.cr.mti<br />+ /fpga/_ver0.00/sim_cdv/sim_cdv.mpf<br />+ /fpga/_ver0.00/sim_cdv/tb.v<br />+ /fpga/_ver0.00/sim_models<br />+ /fpga/_ver0.00/sim_models/drammem.v<br />+ /fpga/_ver0.00/sim_models/ram.v<br />+ /fpga/_ver0.00/sim_models/rom.v<br />+ /fpga/_ver0.00/sim_models/T80.vhd<br />+ /fpga/_ver0.00/sim_models/T80a.vhd<br />+ /fpga/_ver0.00/sim_models/T80_ALU.vhd<br />+ /fpga/_ver0.00/sim_models/T80_MCode.vhd<br />+ /fpga/_ver0.00/sim_models/T80_Pack.vhd<br />+ /fpga/_ver0.00/sim_models/T80_Reg.vhd<br />+ /fpga/_ver0.00/slave<br />+ /fpga/_ver0.00/slave/slavespi.v<br />+ /fpga/_ver0.00/slave/zx.h<br />+ /fpga/_ver0.00/slave/zx_keys.txt<br />+ /fpga/_ver0.00/vg93<br />+ /fpga/_ver0.00/vg93/vg93.v<br />+ /fpga/_ver0.00/video<br />+ /fpga/_ver0.00/video/addresses.txt<br />+ /fpga/_ver0.00/video/fetch.v<br />+ /fpga/_ver0.00/video/synch.v<br />+ /fpga/_ver0.00/video/syncv.v<br />+ /fpga/_ver0.00/video/videoout.v<br />+ /fpga/_ver0.00/video_modes.txt<br />+ /fpga/_ver0.00/z80<br />+ /fpga/_ver0.00/z80/zbus.v<br />+ /fpga/_ver0.00/z80/zclock.v<br />+ /fpga/_ver0.00/z80/zint.v<br />+ /fpga/_ver0.00/z80/zmem.v<br />+ /fpga/_ver0.00/z80/zports.v<br />+ /fpga/_ver0.01<br />+ /fpga/_ver0.01/common<br />+ /fpga/_ver0.01/common/resetter.v<br />+ /fpga/_ver0.01/common/spi2.v<br />+ /fpga/_ver0.01/dram<br />+ /fpga/_ver0.01/dram/arbiter.png<br />+ /fpga/_ver0.01/dram/arbiter.v<br />+ /fpga/_ver0.01/dram/cycles.txt<br />+ /fpga/_ver0.01/dram/dram.v<br />+ /fpga/_ver0.01/dram/test_compile.zip<br />+ /fpga/_ver0.01/include<br />+ /fpga/_ver0.01/include/tune.v<br />+ /fpga/_ver0.01/quartus<br />+ /fpga/_ver0.01/quartus/pentevo_0_01.qpf<br />+ /fpga/_ver0.01/quartus/pentevo_0_01.qws<br />+ /fpga/_ver0.01/quartus/top.qsf<br />+ /fpga/_ver0.01/quartus/top.rbf<br />+ /fpga/_ver0.01/quartus/top.sof<br />+ /fpga/_ver0.01/README<br />+ /fpga/_ver0.01/sim_cdv<br />+ /fpga/_ver0.01/sim_cdv/a<br />+ /fpga/_ver0.01/sim_cdv/b<br />+ /fpga/_ver0.01/sim_cdv/tb.v<br />+ /fpga/_ver0.01/sim_models<br />+ /fpga/_ver0.01/sim_models/drammem.v<br />+ /fpga/_ver0.01/sim_models/ram.v<br />+ /fpga/_ver0.01/sim_models/rom.v<br />+ /fpga/_ver0.01/sim_models/T80.vhd<br />+ /fpga/_ver0.01/sim_models/T80a.vhd<br />+ /fpga/_ver0.01/sim_models/T80_ALU.vhd<br />+ /fpga/_ver0.01/sim_models/T80_MCode.vhd<br />+ /fpga/_ver0.01/sim_models/T80_Pack.vhd<br />+ /fpga/_ver0.01/sim_models/T80_Reg.vhd<br />+ /fpga/_ver0.01/slave<br />+ /fpga/_ver0.01/slave/slavespi.v<br />+ /fpga/_ver0.01/slave/zx.h<br />+ /fpga/_ver0.01/slave/zx_keys.txt<br />+ /fpga/_ver0.01/texts<br />+ /fpga/_ver0.01/texts/dram_access.txt<br />+ /fpga/_ver0.01/texts/readme.txt<br />+ /fpga/_ver0.01/texts/video_modes.txt<br />+ /fpga/_ver0.01/top.v<br />+ /fpga/_ver0.01/vg93<br />+ /fpga/_ver0.01/vg93/vg93.v<br />+ /fpga/_ver0.01/video<br />+ /fpga/_ver0.01/video/addresses.txt<br />+ /fpga/_ver0.01/video/fetch.v<br />+ /fpga/_ver0.01/video/synch.v<br />+ /fpga/_ver0.01/video/syncv.v<br />+ /fpga/_ver0.01/video/videoout.v<br />+ /fpga/_ver0.01/z80<br />+ /fpga/_ver0.01/z80/zbus.v<br />+ /fpga/_ver0.01/z80/zclock.v<br />+ /fpga/_ver0.01/z80/zint.v<br />+ /fpga/_ver0.01/z80/zmem.v<br />+ /fpga/_ver0.01/z80/zports.v<br />http://svn.zxevo.ru/revision.php?repname=pentevo&path=%2Ffpga%2Ftests%2Ftest_dram%2Ftest_dram.qws&rev=4http://svn.zxevo.ru/revision.php?repname=pentevo&path=%2Ffpga%2Ftests%2Ftest_dram%2Ftest_dram.qws&rev=4