<?xml version="1.0" encoding="utf-8"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>ngs &#x2013; /fpga/current/dma/modelsim/wave.bmp</title><description>WebSVN RSS feed &#x2013; ngs</description><lastBuildDate>Tue, 21 Apr 2026 21:56:51 +0300</lastBuildDate><generator>WebSVN 2.8.5-DEV</generator><language>en</language><link>http://svn.zxevo.ru/log.php?repname=ngs&amp;path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;max=20&amp;</link><atom:link href="http://svn.zxevo.ru/rss.php?path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;repname=ngs" rel="self" type="application/rss+xml" />
<item><pubDate>Thu, 25 Nov 2010 00:20:25 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 61 – started refucktoring code and adding new features to FPGA. now ...</title><description>&lt;div&gt;&lt;strong&gt;lvd – 15 file(s) modified&lt;/strong&gt;&lt;br/&gt;started refucktoring code and adding new features to FPGA.&lt;br /&gt;
now fpga/current is head of development (not checked yet)&lt;/div&gt;+ /fpga/current &lt;i&gt;(copied from /fpga/fpgaF_dma2@60)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/common/spi.v &lt;i&gt;(copied from /fpga/fpgaF_dma2/common/spi2.v@60)&lt;/i&gt;&lt;br /&gt;x /fpga/current/common/spi2.v&lt;br /&gt;/fpga/current/dma/dma_zx.v &lt;i&gt;(copied from /fpga/fpgaF_dma2/dma/dma_zx2.v@60)&lt;/i&gt;&lt;br /&gt;x /fpga/current/dma/dma_zx2.v&lt;br /&gt;x /fpga/current/dma/dma_zx_old.v&lt;br /&gt;x /fpga/current/main.v&lt;br /&gt;~ /fpga/current/quartus/main.qsf&lt;br /&gt;x /fpga/current/quartus/main.qws&lt;br /&gt;~ /fpga/current/readme.txt&lt;br /&gt;+ /fpga/current/sound/sound_dac.v &lt;i&gt;(copied from /fpga/fpgaF_dma2/sound/sound_dac2.v@60)&lt;/i&gt;&lt;br /&gt;x /fpga/current/sound/sound_dac2.v&lt;br /&gt;+ /fpga/current/sound/sound_main.v &lt;i&gt;(copied from /fpga/fpgaF_dma2/sound/sound_main2.v@60)&lt;/i&gt;&lt;br /&gt;x /fpga/current/sound/sound_main2.v&lt;br /&gt;+ /fpga/current/top.v &lt;i&gt;(copied from /fpga/fpgaF_dma2/main.v@60)&lt;/i&gt;&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=ngs&amp;path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;rev=61</link><guid>http://svn.zxevo.ru/revision.php?repname=ngs&amp;path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;rev=61</guid></item>
<item><pubDate>Sat, 21 Nov 2009 21:52:10 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 2 – Just files, which all was forgotten in initial commit</title><description>&lt;div&gt;&lt;strong&gt;lvd – 75 file(s) modified&lt;/strong&gt;&lt;br/&gt;Just files, which all was forgotten in initial commit&lt;/div&gt;+ /fpga/fpgaF_dma2&lt;br /&gt;+ /fpga/fpgaF_dma2/common&lt;br /&gt;+ /fpga/fpgaF_dma2/common/mem512b.v&lt;br /&gt;+ /fpga/fpgaF_dma2/common/resetter.v&lt;br /&gt;+ /fpga/fpgaF_dma2/common/spi2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/common/spi2_modelled.png&lt;br /&gt;+ /fpga/fpgaF_dma2/common/spi2_modelled.zip&lt;br /&gt;+ /fpga/fpgaF_dma2/dma&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_access.png&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_access.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_registers.txt&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_sd.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_sequencer.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_sequencer2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_zx.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_zx2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/dma_zx_old.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/dbg1.do&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/dma.cr.mti&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/dma.mpf&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/ram.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/rom.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/t80.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/T80a.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/t80_alu.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/T80_MCode.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/T80_Pack.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/T80_Reg.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/T80_RegX.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.cr.mti&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.do&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.mpf&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.png&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma2.do&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/tb_dma2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/modelsim/wave.bmp&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/rr_arbiter_tb.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/d.do&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/dma_tester.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/rr_arbiter_tb.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/tb_4way.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/tb_dma1.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/tb_dma2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim/wave.do&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/ram.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/rom.v&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/t80.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/T80a.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/t80_alu.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/T80_MCode.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/T80_Pack.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/T80_Reg.vhd&lt;br /&gt;+ /fpga/fpgaF_dma2/dma/sim_models/T80_RegX.vhd_DONT_COMPILE_ME&lt;br /&gt;+ /fpga/fpgaF_dma2/interrupts&lt;br /&gt;+ /fpga/fpgaF_dma2/interrupts/interrupts.v&lt;br /&gt;+ /fpga/fpgaF_dma2/main.v&lt;br /&gt;+ /fpga/fpgaF_dma2/memmap&lt;br /&gt;+ /fpga/fpgaF_dma2/memmap/memmap.v&lt;br /&gt;+ /fpga/fpgaF_dma2/ports&lt;br /&gt;+ /fpga/fpgaF_dma2/ports/ports.v&lt;br /&gt;+ /fpga/fpgaF_dma2/quartus&lt;br /&gt;+ /fpga/fpgaF_dma2/quartus/main.qpf&lt;br /&gt;+ /fpga/fpgaF_dma2/quartus/main.qsf&lt;br /&gt;+ /fpga/fpgaF_dma2/quartus/main.qws&lt;br /&gt;+ /fpga/fpgaF_dma2/readme.txt&lt;br /&gt;+ /fpga/fpgaF_dma2/sound&lt;br /&gt;+ /fpga/fpgaF_dma2/sound/sound_dac2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/sound/sound_main2.v&lt;br /&gt;+ /fpga/fpgaF_dma2/sound/sound_mulacc.v&lt;br /&gt;+ /fpga/fpgaF_dma2/zxbus&lt;br /&gt;+ /fpga/fpgaF_dma2/zxbus/zxbus.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=ngs&amp;path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;rev=2</link><guid>http://svn.zxevo.ru/revision.php?repname=ngs&amp;path=%2Ffpga%2Fcurrent%2Fdma%2Fmodelsim%2Fwave.bmp&amp;rev=2</guid></item>
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