pentevo – /fpga/base_trdemu/newirq/sim_models/T80.vhd

Rev 1319 – pentevo: fpga: make fpga branch to develop new irqs #2

lvd — Sat, 03 Jan 2026 01:52:14 +0300

lvd – 1 file(s) modified
pentevo: fpga: make fpga branch to develop new irqs #2

+ /fpga/base_trdemu/newirq (copied from /fpga/base_trdemu/trunk@1318)

Rev 905 – fpga: trdemu: changing dir structure

lvd — Sun, 15 Nov 2020 16:52:48 +0300

lvd – 10 file(s) modified
fpga: trdemu: changing dir structure

~ /cfgs/standalone_baseconf/trunk/make.sh
+ /fpga/base_trdemu (copied from /fpga/trdemu@904)
+ /fpga/base_trdemu/trunk/doc
+ /fpga/base_trdemu/trunk/doc/zxevo_trdemu.odt (copied from /fpga/trdemu/trunk/zxevo_base_configuration.odt@904)
x /fpga/base_trdemu/trunk/dram/test_compile.zip
~ /fpga/base_trdemu/trunk/video/video_modedecode.v
x /fpga/base_trdemu/trunk/z80/clocking
x /fpga/base_trdemu/trunk/zxevo_base_configuration.odt
x /fpga/base_trdemu/trunk/zxevo_fw.bin
x /fpga/trdemu

Rev 896 – pentevo: changing repo structure

lvd — Sat, 14 Nov 2020 20:24:33 +0300

lvd – 44 file(s) modified
pentevo: changing repo structure

+ /cfgs
+ /cfgs/standalone_baseconf
+ /cfgs/standalone_baseconf/trunk
+ /cfgs/standalone_baseconf/trunk/README
+ /fpga/baseconf
+ /fpga/baseconf/trunk
+ /fpga/baseconf/trunk/common (copied from /fpga/current/common@895)
+ /fpga/baseconf/trunk/dram (copied from /fpga/current/dram@895)
+ /fpga/baseconf/trunk/GPL (copied from /fpga/current/GPL@895)
+ /fpga/baseconf/trunk/include (copied from /fpga/current/include@895)
+ /fpga/baseconf/trunk/mem (copied from /fpga/current/mem@895)
+ /fpga/baseconf/trunk/quartus (copied from /fpga/current/quartus@895)
+ /fpga/baseconf/trunk/sim_models (copied from /fpga/current/sim_models@895)
+ /fpga/baseconf/trunk/sim_top (copied from /fpga/current/sim_top@895)
+ /fpga/baseconf/trunk/slave (copied from /fpga/current/slave@895)
+ /fpga/baseconf/trunk/sound (copied from /fpga/current/sound@895)
+ /fpga/baseconf/trunk/spihub (copied from /fpga/current/spihub@895)
+ /fpga/baseconf/trunk/texts (copied from /fpga/current/texts@895)
+ /fpga/baseconf/trunk/TODO (copied from /fpga/current/TODO@895)
+ /fpga/baseconf/trunk/top.v (copied from /fpga/current/top.v@895)
+ /fpga/baseconf/trunk/ULAPLUS (copied from /fpga/current/ULAPLUS@895)
+ /fpga/baseconf/trunk/vg93 (copied from /fpga/current/vg93@895)
+ /fpga/baseconf/trunk/video (copied from /fpga/current/video@895)
+ /fpga/baseconf/trunk/z80 (copied from /fpga/current/z80@895)
+ /fpga/trdemu/trunk
+ /fpga/trdemu/trunk/common (copied from /fpga/trdemu/common@895)
+ /fpga/trdemu/trunk/dram (copied from /fpga/trdemu/dram@895)
+ /fpga/trdemu/trunk/include (copied from /fpga/trdemu/include@895)
+ /fpga/trdemu/trunk/mem (copied from /fpga/trdemu/mem@895)
+ /fpga/trdemu/trunk/quartus (copied from /fpga/trdemu/quartus@895)
+ /fpga/trdemu/trunk/sim_models (copied from /fpga/trdemu/sim_models@895)
+ /fpga/trdemu/trunk/sim_top (copied from /fpga/trdemu/sim_top@895)
+ /fpga/trdemu/trunk/slave (copied from /fpga/trdemu/slave@895)
+ /fpga/trdemu/trunk/sound (copied from /fpga/trdemu/sound@895)
+ /fpga/trdemu/trunk/spihub (copied from /fpga/trdemu/spihub@895)
+ /fpga/trdemu/trunk/texts (copied from /fpga/trdemu/texts@895)
+ /fpga/trdemu/trunk/TODO (copied from /fpga/trdemu/TODO@895)
+ /fpga/trdemu/trunk/top.v (copied from /fpga/trdemu/top.v@895)
+ /fpga/trdemu/trunk/ULAPLUS (copied from /fpga/trdemu/ULAPLUS@895)
+ /fpga/trdemu/trunk/vg93 (copied from /fpga/trdemu/vg93@895)
+ /fpga/trdemu/trunk/video (copied from /fpga/trdemu/video@895)
+ /fpga/trdemu/trunk/z80 (copied from /fpga/trdemu/z80@895)
+ /fpga/trdemu/trunk/zxevo_base_configuration.odt (copied from /fpga/trdemu/zxevo_base_configuration.odt@895)
+ /fpga/trdemu/trunk/zxevo_fw.bin (copied from /fpga/trdemu/zxevo_fw.bin@895)

Rev 849 – spawned a branch, added fdd mask register

lvd — Thu, 09 Jan 2020 23:16:31 +0300

lvd – 5 file(s) modified
spawned a branch, added fdd mask register

+ /fpga/trdemu (copied from /fpga/current@848)
~ /fpga/trdemu/slave/slavespi.v
~ /fpga/trdemu/slave/spi_fmt.txt
~ /fpga/trdemu/top.v
~ /fpga/trdemu/z80/zports.v

Rev 684 – updated srcs for ULA emulation

lvd — Tue, 13 Jan 2015 17:53:16 +0300

lvd – 25 file(s) modified
updated srcs for ULA emulation

~ /avr/current/main.h
~ /avr/current/zx.c
~ /fpga/current/mem/atm_pager.v
+ /fpga/current/sim_models/cmosemu.v
~ /fpga/current/sim_models/T80.vhd
~ /fpga/current/sim_models/T80a.vhd
~ /fpga/current/sim_models/T80_Pack.vhd
+ /fpga/current/sim_top/c48k
+ /fpga/current/sim_top/ccontend
+ /fpga/current/sim_top/dw5.bin
~ /fpga/current/sim_top/Makefile
~ /fpga/current/sim_top/sc
~ /fpga/current/sim_top/tb_top.v
~ /fpga/current/sim_top/vlog.opt
~ /fpga/current/sim_top/wave.do
~ /fpga/current/top.v
~ /fpga/current/video/video_palframe.v
~ /fpga/current/video/video_sync_h.v
~ /fpga/current/video/video_sync_v.v
~ /fpga/current/video/video_top.v
~ /fpga/current/video/video_vga_sync_h.v
~ /fpga/current/z80/zclock.v
~ /fpga/current/z80/zmem.v
~ /fpga/current/z80/zports.v
~ /fpga/current/z80/zwait.v

Rev 4 – initial commit of FPGA files

lvd — Sat, 21 Nov 2009 21:06:56 +0300

lvd – 195 file(s) modified
initial commit of FPGA files

x /file1st
+ /fpga
+ /fpga/current
+ /fpga/current/common
+ /fpga/current/common/resetter.v
+ /fpga/current/common/spi2.v
+ /fpga/current/dram
+ /fpga/current/dram/arbiter.png
+ /fpga/current/dram/arbiter.v
+ /fpga/current/dram/cycles.txt
+ /fpga/current/dram/dram.v
+ /fpga/current/dram/test_compile.zip
+ /fpga/current/include
+ /fpga/current/include/tune.v
+ /fpga/current/quartus
+ /fpga/current/quartus/pentevo_0_01.qpf
+ /fpga/current/quartus/pentevo_0_01.qws
+ /fpga/current/quartus/top.qsf
+ /fpga/current/quartus/top.rbf
+ /fpga/current/quartus/top.sof
+ /fpga/current/quartus/top_fix_ide_maybe.zip
+ /fpga/current/README
+ /fpga/current/sim_cdv
+ /fpga/current/sim_cdv/a
+ /fpga/current/sim_cdv/b
+ /fpga/current/sim_cdv/tb.v
+ /fpga/current/sim_models
+ /fpga/current/sim_models/drammem.v
+ /fpga/current/sim_models/ram.v
+ /fpga/current/sim_models/rom.v
+ /fpga/current/sim_models/T80.vhd
+ /fpga/current/sim_models/T80a.vhd
+ /fpga/current/sim_models/T80_ALU.vhd
+ /fpga/current/sim_models/T80_MCode.vhd
+ /fpga/current/sim_models/T80_Pack.vhd
+ /fpga/current/sim_models/T80_Reg.vhd
+ /fpga/current/slave
+ /fpga/current/slave/slavespi.v
+ /fpga/current/slave/zx.h
+ /fpga/current/slave/zx_keys.txt
+ /fpga/current/texts
+ /fpga/current/texts/dram_access.txt
+ /fpga/current/texts/readme.txt
+ /fpga/current/texts/video_modes.txt
+ /fpga/current/top.v
+ /fpga/current/vg93
+ /fpga/current/vg93/vg93.v
+ /fpga/current/video
+ /fpga/current/video/addresses.txt
+ /fpga/current/video/fetch.v
+ /fpga/current/video/synch.v
+ /fpga/current/video/syncv.v
+ /fpga/current/video/videoout.v
+ /fpga/current/z80
+ /fpga/current/z80/zbus.v
+ /fpga/current/z80/zclock.v
+ /fpga/current/z80/zint.v
+ /fpga/current/z80/zmem.v
+ /fpga/current/z80/zports.v
+ /fpga/tests
+ /fpga/tests/test_dram
+ /fpga/tests/test_dram/dram.v
+ /fpga/tests/test_dram/dram_control.v
+ /fpga/tests/test_dram/main.qsf
+ /fpga/tests/test_dram/main.rbf
+ /fpga/tests/test_dram/main.sof
+ /fpga/tests/test_dram/main.v
+ /fpga/tests/test_dram/main_.v
+ /fpga/tests/test_dram/mem_tester.v
+ /fpga/tests/test_dram/resetter.v
+ /fpga/tests/test_dram/rnd_vec_gen.v
+ /fpga/tests/test_dram/sram_control.v
+ /fpga/tests/test_dram/stable.sof
+ /fpga/tests/test_dram/test_dram.qpf
+ /fpga/tests/test_dram/test_dram.qws
+ /fpga/tests/test_ledblink
+ /fpga/tests/test_ledblink/dram.v
+ /fpga/tests/test_ledblink/main.qsf
+ /fpga/tests/test_ledblink/main.v
+ /fpga/tests/test_ledblink/stable.sof
+ /fpga/tests/test_ledblink/test_ledblink.qpf
+ /fpga/tests/test_ledblink/test_ledblink.qws
+ /fpga/_ver0.00
+ /fpga/_ver0.00/common
+ /fpga/_ver0.00/common/resetter.v
+ /fpga/_ver0.00/common/spi2.v
+ /fpga/_ver0.00/dram
+ /fpga/_ver0.00/dram/arbiter.png
+ /fpga/_ver0.00/dram/arbiter.v
+ /fpga/_ver0.00/dram/cycles.txt
+ /fpga/_ver0.00/dram/dram.v
+ /fpga/_ver0.00/dram/test_compile
+ /fpga/_ver0.00/dram/test_compile/arbiter.cvwf
+ /fpga/_ver0.00/dram/test_compile/arbiter.qsf
+ /fpga/_ver0.00/dram/test_compile/arbiter_description.txt
+ /fpga/_ver0.00/dram/test_compile/test_compile.qpf
+ /fpga/_ver0.00/dram/test_compile/test_compile.qws
+ /fpga/_ver0.00/dram/test_compile/test_compile.v
+ /fpga/_ver0.00/dram_access.txt
+ /fpga/_ver0.00/include
+ /fpga/_ver0.00/include/tune.v
+ /fpga/_ver0.00/keyboard
+ /fpga/_ver0.00/main.v
+ /fpga/_ver0.00/readme.txt
+ /fpga/_ver0.00/sim_cdv
+ /fpga/_ver0.00/sim_cdv/a
+ /fpga/_ver0.00/sim_cdv/b
+ /fpga/_ver0.00/sim_cdv/sim_cdv.cr.mti
+ /fpga/_ver0.00/sim_cdv/sim_cdv.mpf
+ /fpga/_ver0.00/sim_cdv/tb.v
+ /fpga/_ver0.00/sim_models
+ /fpga/_ver0.00/sim_models/drammem.v
+ /fpga/_ver0.00/sim_models/ram.v
+ /fpga/_ver0.00/sim_models/rom.v
+ /fpga/_ver0.00/sim_models/T80.vhd
+ /fpga/_ver0.00/sim_models/T80a.vhd
+ /fpga/_ver0.00/sim_models/T80_ALU.vhd
+ /fpga/_ver0.00/sim_models/T80_MCode.vhd
+ /fpga/_ver0.00/sim_models/T80_Pack.vhd
+ /fpga/_ver0.00/sim_models/T80_Reg.vhd
+ /fpga/_ver0.00/slave
+ /fpga/_ver0.00/slave/slavespi.v
+ /fpga/_ver0.00/slave/zx.h
+ /fpga/_ver0.00/slave/zx_keys.txt
+ /fpga/_ver0.00/vg93
+ /fpga/_ver0.00/vg93/vg93.v
+ /fpga/_ver0.00/video
+ /fpga/_ver0.00/video/addresses.txt
+ /fpga/_ver0.00/video/fetch.v
+ /fpga/_ver0.00/video/synch.v
+ /fpga/_ver0.00/video/syncv.v
+ /fpga/_ver0.00/video/videoout.v
+ /fpga/_ver0.00/video_modes.txt
+ /fpga/_ver0.00/z80
+ /fpga/_ver0.00/z80/zbus.v
+ /fpga/_ver0.00/z80/zclock.v
+ /fpga/_ver0.00/z80/zint.v
+ /fpga/_ver0.00/z80/zmem.v
+ /fpga/_ver0.00/z80/zports.v
+ /fpga/_ver0.01
+ /fpga/_ver0.01/common
+ /fpga/_ver0.01/common/resetter.v
+ /fpga/_ver0.01/common/spi2.v
+ /fpga/_ver0.01/dram
+ /fpga/_ver0.01/dram/arbiter.png
+ /fpga/_ver0.01/dram/arbiter.v
+ /fpga/_ver0.01/dram/cycles.txt
+ /fpga/_ver0.01/dram/dram.v
+ /fpga/_ver0.01/dram/test_compile.zip
+ /fpga/_ver0.01/include
+ /fpga/_ver0.01/include/tune.v
+ /fpga/_ver0.01/quartus
+ /fpga/_ver0.01/quartus/pentevo_0_01.qpf
+ /fpga/_ver0.01/quartus/pentevo_0_01.qws
+ /fpga/_ver0.01/quartus/top.qsf
+ /fpga/_ver0.01/quartus/top.rbf
+ /fpga/_ver0.01/quartus/top.sof
+ /fpga/_ver0.01/README
+ /fpga/_ver0.01/sim_cdv
+ /fpga/_ver0.01/sim_cdv/a
+ /fpga/_ver0.01/sim_cdv/b
+ /fpga/_ver0.01/sim_cdv/tb.v
+ /fpga/_ver0.01/sim_models
+ /fpga/_ver0.01/sim_models/drammem.v
+ /fpga/_ver0.01/sim_models/ram.v
+ /fpga/_ver0.01/sim_models/rom.v
+ /fpga/_ver0.01/sim_models/T80.vhd
+ /fpga/_ver0.01/sim_models/T80a.vhd
+ /fpga/_ver0.01/sim_models/T80_ALU.vhd
+ /fpga/_ver0.01/sim_models/T80_MCode.vhd
+ /fpga/_ver0.01/sim_models/T80_Pack.vhd
+ /fpga/_ver0.01/sim_models/T80_Reg.vhd
+ /fpga/_ver0.01/slave
+ /fpga/_ver0.01/slave/slavespi.v
+ /fpga/_ver0.01/slave/zx.h
+ /fpga/_ver0.01/slave/zx_keys.txt
+ /fpga/_ver0.01/texts
+ /fpga/_ver0.01/texts/dram_access.txt
+ /fpga/_ver0.01/texts/readme.txt
+ /fpga/_ver0.01/texts/video_modes.txt
+ /fpga/_ver0.01/top.v
+ /fpga/_ver0.01/vg93
+ /fpga/_ver0.01/vg93/vg93.v
+ /fpga/_ver0.01/video
+ /fpga/_ver0.01/video/addresses.txt
+ /fpga/_ver0.01/video/fetch.v
+ /fpga/_ver0.01/video/synch.v
+ /fpga/_ver0.01/video/syncv.v
+ /fpga/_ver0.01/video/videoout.v
+ /fpga/_ver0.01/z80
+ /fpga/_ver0.01/z80/zbus.v
+ /fpga/_ver0.01/z80/zclock.v
+ /fpga/_ver0.01/z80/zint.v
+ /fpga/_ver0.01/z80/zmem.v
+ /fpga/_ver0.01/z80/zports.v