<?xml version="1.0" encoding="utf-8"?><rss version="2.0" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>pentevo &#x2013; /fpga/base_trdemu/newirq/common/</title><description>WebSVN RSS feed &#x2013; pentevo</description><lastBuildDate>Thu, 16 Apr 2026 16:32:16 +0300</lastBuildDate><generator>WebSVN 2.8.5-DEV</generator><language>en</language><link>http://svn.zxevo.ru/log.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;max=20&amp;</link><atom:link href="http://svn.zxevo.ru/rss.php?repname=pentevo&amp;path=/fpga/base_trdemu/newirq/common/&amp;isdir=1&amp;" rel="self" type="application/rss+xml" />
<item><pubDate>Sat, 03 Jan 2026 01:52:14 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 1319 – pentevo: fpga: make fpga branch to develop new irqs #2</title><description>&lt;div&gt;&lt;strong&gt;lvd – 1 file(s) modified&lt;/strong&gt;&lt;br/&gt;pentevo: fpga: make fpga branch to develop new irqs #2&lt;/div&gt;+ /fpga/base_trdemu/newirq &lt;i&gt;(copied from /fpga/base_trdemu/trunk@1318)&lt;/i&gt;&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=1319</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=1319</guid></item>
<item><pubDate>Sun, 15 Nov 2020 16:52:48 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 905 – fpga: trdemu: changing dir structure</title><description>&lt;div&gt;&lt;strong&gt;lvd – 10 file(s) modified&lt;/strong&gt;&lt;br/&gt;fpga: trdemu: changing dir structure&lt;/div&gt;~ /cfgs/standalone_baseconf/trunk/make.sh&lt;br /&gt;+ /fpga/base_trdemu &lt;i&gt;(copied from /fpga/trdemu@904)&lt;/i&gt;&lt;br /&gt;+ /fpga/base_trdemu/trunk/doc&lt;br /&gt;+ /fpga/base_trdemu/trunk/doc/zxevo_trdemu.odt &lt;i&gt;(copied from /fpga/trdemu/trunk/zxevo_base_configuration.odt@904)&lt;/i&gt;&lt;br /&gt;x /fpga/base_trdemu/trunk/dram/test_compile.zip&lt;br /&gt;~ /fpga/base_trdemu/trunk/video/video_modedecode.v&lt;br /&gt;x /fpga/base_trdemu/trunk/z80/clocking&lt;br /&gt;x /fpga/base_trdemu/trunk/zxevo_base_configuration.odt&lt;br /&gt;x /fpga/base_trdemu/trunk/zxevo_fw.bin&lt;br /&gt;x /fpga/trdemu&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=905</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=905</guid></item>
<item><pubDate>Sat, 14 Nov 2020 20:24:33 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 896 – pentevo: changing repo structure</title><description>&lt;div&gt;&lt;strong&gt;lvd – 44 file(s) modified&lt;/strong&gt;&lt;br/&gt;pentevo: changing repo structure&lt;/div&gt;+ /cfgs&lt;br /&gt;+ /cfgs/standalone_baseconf&lt;br /&gt;+ /cfgs/standalone_baseconf/trunk&lt;br /&gt;+ /cfgs/standalone_baseconf/trunk/README&lt;br /&gt;+ /fpga/baseconf&lt;br /&gt;+ /fpga/baseconf/trunk&lt;br /&gt;+ /fpga/baseconf/trunk/common &lt;i&gt;(copied from /fpga/current/common@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/dram &lt;i&gt;(copied from /fpga/current/dram@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/GPL &lt;i&gt;(copied from /fpga/current/GPL@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/include &lt;i&gt;(copied from /fpga/current/include@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/mem &lt;i&gt;(copied from /fpga/current/mem@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/quartus &lt;i&gt;(copied from /fpga/current/quartus@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/sim_models &lt;i&gt;(copied from /fpga/current/sim_models@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/sim_top &lt;i&gt;(copied from /fpga/current/sim_top@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/slave &lt;i&gt;(copied from /fpga/current/slave@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/sound &lt;i&gt;(copied from /fpga/current/sound@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/spihub &lt;i&gt;(copied from /fpga/current/spihub@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/texts &lt;i&gt;(copied from /fpga/current/texts@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/TODO &lt;i&gt;(copied from /fpga/current/TODO@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/top.v &lt;i&gt;(copied from /fpga/current/top.v@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/ULAPLUS &lt;i&gt;(copied from /fpga/current/ULAPLUS@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/vg93 &lt;i&gt;(copied from /fpga/current/vg93@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/video &lt;i&gt;(copied from /fpga/current/video@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/baseconf/trunk/z80 &lt;i&gt;(copied from /fpga/current/z80@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk&lt;br /&gt;+ /fpga/trdemu/trunk/common &lt;i&gt;(copied from /fpga/trdemu/common@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/dram &lt;i&gt;(copied from /fpga/trdemu/dram@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/include &lt;i&gt;(copied from /fpga/trdemu/include@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/mem &lt;i&gt;(copied from /fpga/trdemu/mem@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/quartus &lt;i&gt;(copied from /fpga/trdemu/quartus@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/sim_models &lt;i&gt;(copied from /fpga/trdemu/sim_models@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/sim_top &lt;i&gt;(copied from /fpga/trdemu/sim_top@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/slave &lt;i&gt;(copied from /fpga/trdemu/slave@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/sound &lt;i&gt;(copied from /fpga/trdemu/sound@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/spihub &lt;i&gt;(copied from /fpga/trdemu/spihub@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/texts &lt;i&gt;(copied from /fpga/trdemu/texts@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/TODO &lt;i&gt;(copied from /fpga/trdemu/TODO@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/top.v &lt;i&gt;(copied from /fpga/trdemu/top.v@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/ULAPLUS &lt;i&gt;(copied from /fpga/trdemu/ULAPLUS@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/vg93 &lt;i&gt;(copied from /fpga/trdemu/vg93@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/video &lt;i&gt;(copied from /fpga/trdemu/video@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/z80 &lt;i&gt;(copied from /fpga/trdemu/z80@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/zxevo_base_configuration.odt &lt;i&gt;(copied from /fpga/trdemu/zxevo_base_configuration.odt@895)&lt;/i&gt;&lt;br /&gt;+ /fpga/trdemu/trunk/zxevo_fw.bin &lt;i&gt;(copied from /fpga/trdemu/zxevo_fw.bin@895)&lt;/i&gt;&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=896</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=896</guid></item>
<item><pubDate>Thu, 09 Jan 2020 23:16:31 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 849 – spawned a branch, added fdd mask register</title><description>&lt;div&gt;&lt;strong&gt;lvd – 5 file(s) modified&lt;/strong&gt;&lt;br/&gt;spawned a branch, added fdd mask register&lt;/div&gt;+ /fpga/trdemu &lt;i&gt;(copied from /fpga/current@848)&lt;/i&gt;&lt;br /&gt;~ /fpga/trdemu/slave/slavespi.v&lt;br /&gt;~ /fpga/trdemu/slave/spi_fmt.txt&lt;br /&gt;~ /fpga/trdemu/top.v&lt;br /&gt;~ /fpga/trdemu/z80/zports.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=849</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=849</guid></item>
<item><pubDate>Tue, 29 Jul 2014 10:01:19 +0400</pubDate><dc:creator>lvd</dc:creator><title>Rev 668 – pentevo: added ulaplus, fixed NMI to RAM (DimkaM request)</title><description>&lt;div&gt;&lt;strong&gt;lvd – 44 file(s) modified&lt;/strong&gt;&lt;br/&gt;pentevo: added ulaplus, fixed NMI to RAM (DimkaM request)&lt;/div&gt;~ /avr/current/default/core.hex&lt;br /&gt;~ /avr/current/default/zxevo_fw.bin&lt;br /&gt;~ /fpga/current/common/resetter.v&lt;br /&gt;~ /fpga/current/dram/arbiter.v&lt;br /&gt;~ /fpga/current/dram/dram.v&lt;br /&gt;x /fpga/current/FIXME&lt;br /&gt;+ /fpga/current/GPL&lt;br /&gt;~ /fpga/current/include/tune.v&lt;br /&gt;~ /fpga/current/mem/atm_pager.v&lt;br /&gt;~ /fpga/current/quartus/top.rbf&lt;br /&gt;~ /fpga/current/quartus/top.sof&lt;br /&gt;x /fpga/current/README&lt;br /&gt;~ /fpga/current/slave/slavespi.v&lt;br /&gt;~ /fpga/current/sound/sound.v&lt;br /&gt;~ /fpga/current/spihub/spi2.v&lt;br /&gt;~ /fpga/current/spihub/spihub.v&lt;br /&gt;x /fpga/current/TODO&lt;br /&gt;~ /fpga/current/top.v&lt;br /&gt;+ /fpga/current/ULAPLUS&lt;br /&gt;~ /fpga/current/vg93/fapch_counter.v&lt;br /&gt;~ /fpga/current/vg93/fapch_zek.v&lt;br /&gt;~ /fpga/current/vg93/vg93.v&lt;br /&gt;x /fpga/current/vga&lt;br /&gt;~ /fpga/current/video/video_addrgen.v&lt;br /&gt;~ /fpga/current/video/video_fetch.v&lt;br /&gt;~ /fpga/current/video/video_modedecode.v&lt;br /&gt;~ /fpga/current/video/video_outmux.v&lt;br /&gt;~ /fpga/current/video/video_palframe.v&lt;br /&gt;~ /fpga/current/video/video_render.v&lt;br /&gt;~ /fpga/current/video/video_sync_h.v&lt;br /&gt;~ /fpga/current/video/video_sync_v.v&lt;br /&gt;~ /fpga/current/video/video_top.v&lt;br /&gt;~ /fpga/current/video/video_vga_double.v&lt;br /&gt;~ /fpga/current/video/video_vga_sync_h.v&lt;br /&gt;~ /fpga/current/z80/zbreak.v&lt;br /&gt;~ /fpga/current/z80/zbus.v&lt;br /&gt;~ /fpga/current/z80/zclock.v&lt;br /&gt;~ /fpga/current/z80/zdos.v&lt;br /&gt;~ /fpga/current/z80/zint.v&lt;br /&gt;~ /fpga/current/z80/zkbdmus.v&lt;br /&gt;~ /fpga/current/z80/zmem.v&lt;br /&gt;~ /fpga/current/z80/znmi.v&lt;br /&gt;~ /fpga/current/z80/zports.v&lt;br /&gt;~ /fpga/current/z80/zwait.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=668</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=668</guid></item>
<item><pubDate>Sun, 15 Jan 2012 23:09:23 +0400</pubDate><dc:creator>lvd</dc:creator><title>Rev 543 – fpga/current: merged all features to current (avr sdcard access, updated ...</title><description>&lt;div&gt;&lt;strong&gt;lvd – 30 file(s) modified&lt;/strong&gt;&lt;br/&gt;fpga/current: merged all features to current (avr sdcard access, updated NMI behavior, font read, some bugfixes), built new zxevo_fw.bin&lt;/div&gt;~ /avr/current/default/core.hex&lt;br /&gt;~ /avr/current/default/zxevo_fw.bin&lt;br /&gt;~ /fpga/current&lt;br /&gt;x /fpga/current/common/spi2.v&lt;br /&gt;~ /fpga/current/quartus/top.qsf&lt;br /&gt;~ /fpga/current/quartus/top.rbf&lt;br /&gt;~ /fpga/current/quartus/top.sof&lt;br /&gt;~ /fpga/current/sim_top/c&lt;br /&gt;+ /fpga/current/sim_top/nmitest.bin &lt;i&gt;(copied from /fpga/vmodes/sim_top/nmitest.bin@542)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/nmitest.src &lt;i&gt;(copied from /fpga/vmodes/sim_top/nmitest.src@542)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/nmitest_rom.v &lt;i&gt;(copied from /fpga/vmodes/sim_top/nmitest_rom.v@542)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/sim_top/rom_top.v&lt;br /&gt;+ /fpga/current/sim_top/spitest.bin &lt;i&gt;(copied from /fpga/vmodes/sim_top/spitest.bin@542)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/spitest_avr.v &lt;i&gt;(copied from /fpga/vmodes/sim_top/spitest_avr.v@542)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/spitest_print.v &lt;i&gt;(copied from /fpga/vmodes/sim_top/spitest_print.v@542)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/spitest_rom.v &lt;i&gt;(copied from /fpga/vmodes/sim_top/spitest_rom.v@542)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/sim_top/tb_top.v&lt;br /&gt;~ /fpga/current/sim_top/vlog.opt&lt;br /&gt;~ /fpga/current/sim_top/wave.do&lt;br /&gt;~ /fpga/current/slave/slavespi.v&lt;br /&gt;~ /fpga/current/slave/spi_fmt.txt&lt;br /&gt;+ /fpga/current/spihub &lt;i&gt;(copied from /fpga/vmodes/spihub@542)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/TODO&lt;br /&gt;~ /fpga/current/top.v&lt;br /&gt;~ /fpga/current/video/video_addrgen.v&lt;br /&gt;~ /fpga/current/video/video_modedecode.v&lt;br /&gt;~ /fpga/current/video/video_render.v&lt;br /&gt;~ /fpga/current/video/video_top.v&lt;br /&gt;~ /fpga/current/z80/znmi.v&lt;br /&gt;~ /fpga/current/z80/zports.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=543</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=543</guid></item>
<item><pubDate>Sun, 05 Jun 2011 17:12:18 +0400</pubDate><dc:creator>lvd</dc:creator><title>Rev 425 – atm_nmi merging with current</title><description>&lt;div&gt;&lt;strong&gt;lvd – 35 file(s) modified&lt;/strong&gt;&lt;br/&gt;atm_nmi merging with current&lt;/div&gt;~ /fpga/current&lt;br /&gt;~ /fpga/current/common/resetter.v&lt;br /&gt;~ /fpga/current/dram/dram.v&lt;br /&gt;~ /fpga/current/mem/atm_pager.v&lt;br /&gt;~ /fpga/current/quartus/top.qsf&lt;br /&gt;~ /fpga/current/quartus/top.rbf&lt;br /&gt;~ /fpga/current/quartus/top.sof&lt;br /&gt;~ /fpga/current/sim_top/c&lt;br /&gt;~ /fpga/current/sim_top/d&lt;br /&gt;x /fpga/current/sim_top/l&lt;br /&gt;+ /fpga/current/sim_top/Makefile &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/Makefile@424)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/pixer.v &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/pixer.v@424)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/sim_top/rom_top.v&lt;br /&gt;x /fpga/current/sim_top/s&lt;br /&gt;+ /fpga/current/sim_top/sc &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/sc@424)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/sg &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/sg@424)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/sndpix.c &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/sndpix.c@424)&lt;/i&gt;&lt;br /&gt;+ /fpga/current/sim_top/sndpix.h &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/sndpix.h@424)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/sim_top/tb_top.v&lt;br /&gt;+ /fpga/current/sim_top/viewer.c &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/viewer.c@424)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/sim_top/vlog.opt&lt;br /&gt;~ /fpga/current/sim_top/wave.do&lt;br /&gt;+ /fpga/current/sim_top/zxevo_rom.v &lt;i&gt;(copied from /fpga/atm_nmi/sim_top/zxevo_rom.v@424)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/slave/slavespi.v&lt;br /&gt;~ /fpga/current/top.v&lt;br /&gt;~ /fpga/current/video/video_fontrom.v&lt;br /&gt;~ /fpga/current/video/video_palframe.v&lt;br /&gt;~ /fpga/current/video/video_sync_h.v&lt;br /&gt;~ /fpga/current/video/video_top.v&lt;br /&gt;~ /fpga/current/z80/none.txt&lt;br /&gt;~ /fpga/current/z80/zclock.v&lt;br /&gt;~ /fpga/current/z80/zint.v&lt;br /&gt;+ /fpga/current/z80/znmi.v &lt;i&gt;(copied from /fpga/atm_nmi/z80/znmi.v@424)&lt;/i&gt;&lt;br /&gt;~ /fpga/current/z80/zports.v&lt;br /&gt;~ /fpga/current/z80/zwait.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=425</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=425</guid></item>
<item><pubDate>Thu, 03 Dec 2009 21:59:28 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 32 – resetter.v fixed for simulation</title><description>&lt;div&gt;&lt;strong&gt;lvd – 1 file(s) modified&lt;/strong&gt;&lt;br/&gt;resetter.v fixed for simulation&lt;/div&gt;~ /fpga/current/common/resetter.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=32</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=32</guid></item>
<item><pubDate>Sat, 21 Nov 2009 21:06:56 +0300</pubDate><dc:creator>lvd</dc:creator><title>Rev 4 – initial commit of FPGA files</title><description>&lt;div&gt;&lt;strong&gt;lvd – 195 file(s) modified&lt;/strong&gt;&lt;br/&gt;initial commit of FPGA files&lt;/div&gt;x /file1st&lt;br /&gt;+ /fpga&lt;br /&gt;+ /fpga/current&lt;br /&gt;+ /fpga/current/common&lt;br /&gt;+ /fpga/current/common/resetter.v&lt;br /&gt;+ /fpga/current/common/spi2.v&lt;br /&gt;+ /fpga/current/dram&lt;br /&gt;+ /fpga/current/dram/arbiter.png&lt;br /&gt;+ /fpga/current/dram/arbiter.v&lt;br /&gt;+ /fpga/current/dram/cycles.txt&lt;br /&gt;+ /fpga/current/dram/dram.v&lt;br /&gt;+ /fpga/current/dram/test_compile.zip&lt;br /&gt;+ /fpga/current/include&lt;br /&gt;+ /fpga/current/include/tune.v&lt;br /&gt;+ /fpga/current/quartus&lt;br /&gt;+ /fpga/current/quartus/pentevo_0_01.qpf&lt;br /&gt;+ /fpga/current/quartus/pentevo_0_01.qws&lt;br /&gt;+ /fpga/current/quartus/top.qsf&lt;br /&gt;+ /fpga/current/quartus/top.rbf&lt;br /&gt;+ /fpga/current/quartus/top.sof&lt;br /&gt;+ /fpga/current/quartus/top_fix_ide_maybe.zip&lt;br /&gt;+ /fpga/current/README&lt;br /&gt;+ /fpga/current/sim_cdv&lt;br /&gt;+ /fpga/current/sim_cdv/a&lt;br /&gt;+ /fpga/current/sim_cdv/b&lt;br /&gt;+ /fpga/current/sim_cdv/tb.v&lt;br /&gt;+ /fpga/current/sim_models&lt;br /&gt;+ /fpga/current/sim_models/drammem.v&lt;br /&gt;+ /fpga/current/sim_models/ram.v&lt;br /&gt;+ /fpga/current/sim_models/rom.v&lt;br /&gt;+ /fpga/current/sim_models/T80.vhd&lt;br /&gt;+ /fpga/current/sim_models/T80a.vhd&lt;br /&gt;+ /fpga/current/sim_models/T80_ALU.vhd&lt;br /&gt;+ /fpga/current/sim_models/T80_MCode.vhd&lt;br /&gt;+ /fpga/current/sim_models/T80_Pack.vhd&lt;br /&gt;+ /fpga/current/sim_models/T80_Reg.vhd&lt;br /&gt;+ /fpga/current/slave&lt;br /&gt;+ /fpga/current/slave/slavespi.v&lt;br /&gt;+ /fpga/current/slave/zx.h&lt;br /&gt;+ /fpga/current/slave/zx_keys.txt&lt;br /&gt;+ /fpga/current/texts&lt;br /&gt;+ /fpga/current/texts/dram_access.txt&lt;br /&gt;+ /fpga/current/texts/readme.txt&lt;br /&gt;+ /fpga/current/texts/video_modes.txt&lt;br /&gt;+ /fpga/current/top.v&lt;br /&gt;+ /fpga/current/vg93&lt;br /&gt;+ /fpga/current/vg93/vg93.v&lt;br /&gt;+ /fpga/current/video&lt;br /&gt;+ /fpga/current/video/addresses.txt&lt;br /&gt;+ /fpga/current/video/fetch.v&lt;br /&gt;+ /fpga/current/video/synch.v&lt;br /&gt;+ /fpga/current/video/syncv.v&lt;br /&gt;+ /fpga/current/video/videoout.v&lt;br /&gt;+ /fpga/current/z80&lt;br /&gt;+ /fpga/current/z80/zbus.v&lt;br /&gt;+ /fpga/current/z80/zclock.v&lt;br /&gt;+ /fpga/current/z80/zint.v&lt;br /&gt;+ /fpga/current/z80/zmem.v&lt;br /&gt;+ /fpga/current/z80/zports.v&lt;br /&gt;+ /fpga/tests&lt;br /&gt;+ /fpga/tests/test_dram&lt;br /&gt;+ /fpga/tests/test_dram/dram.v&lt;br /&gt;+ /fpga/tests/test_dram/dram_control.v&lt;br /&gt;+ /fpga/tests/test_dram/main.qsf&lt;br /&gt;+ /fpga/tests/test_dram/main.rbf&lt;br /&gt;+ /fpga/tests/test_dram/main.sof&lt;br /&gt;+ /fpga/tests/test_dram/main.v&lt;br /&gt;+ /fpga/tests/test_dram/main_.v&lt;br /&gt;+ /fpga/tests/test_dram/mem_tester.v&lt;br /&gt;+ /fpga/tests/test_dram/resetter.v&lt;br /&gt;+ /fpga/tests/test_dram/rnd_vec_gen.v&lt;br /&gt;+ /fpga/tests/test_dram/sram_control.v&lt;br /&gt;+ /fpga/tests/test_dram/stable.sof&lt;br /&gt;+ /fpga/tests/test_dram/test_dram.qpf&lt;br /&gt;+ /fpga/tests/test_dram/test_dram.qws&lt;br /&gt;+ /fpga/tests/test_ledblink&lt;br /&gt;+ /fpga/tests/test_ledblink/dram.v&lt;br /&gt;+ /fpga/tests/test_ledblink/main.qsf&lt;br /&gt;+ /fpga/tests/test_ledblink/main.v&lt;br /&gt;+ /fpga/tests/test_ledblink/stable.sof&lt;br /&gt;+ /fpga/tests/test_ledblink/test_ledblink.qpf&lt;br /&gt;+ /fpga/tests/test_ledblink/test_ledblink.qws&lt;br /&gt;+ /fpga/_ver0.00&lt;br /&gt;+ /fpga/_ver0.00/common&lt;br /&gt;+ /fpga/_ver0.00/common/resetter.v&lt;br /&gt;+ /fpga/_ver0.00/common/spi2.v&lt;br /&gt;+ /fpga/_ver0.00/dram&lt;br /&gt;+ /fpga/_ver0.00/dram/arbiter.png&lt;br /&gt;+ /fpga/_ver0.00/dram/arbiter.v&lt;br /&gt;+ /fpga/_ver0.00/dram/cycles.txt&lt;br /&gt;+ /fpga/_ver0.00/dram/dram.v&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/arbiter.cvwf&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/arbiter.qsf&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/arbiter_description.txt&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/test_compile.qpf&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/test_compile.qws&lt;br /&gt;+ /fpga/_ver0.00/dram/test_compile/test_compile.v&lt;br /&gt;+ /fpga/_ver0.00/dram_access.txt&lt;br /&gt;+ /fpga/_ver0.00/include&lt;br /&gt;+ /fpga/_ver0.00/include/tune.v&lt;br /&gt;+ /fpga/_ver0.00/keyboard&lt;br /&gt;+ /fpga/_ver0.00/main.v&lt;br /&gt;+ /fpga/_ver0.00/readme.txt&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv/a&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv/b&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv/sim_cdv.cr.mti&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv/sim_cdv.mpf&lt;br /&gt;+ /fpga/_ver0.00/sim_cdv/tb.v&lt;br /&gt;+ /fpga/_ver0.00/sim_models&lt;br /&gt;+ /fpga/_ver0.00/sim_models/drammem.v&lt;br /&gt;+ /fpga/_ver0.00/sim_models/ram.v&lt;br /&gt;+ /fpga/_ver0.00/sim_models/rom.v&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80.vhd&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80a.vhd&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80_ALU.vhd&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80_MCode.vhd&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80_Pack.vhd&lt;br /&gt;+ /fpga/_ver0.00/sim_models/T80_Reg.vhd&lt;br /&gt;+ /fpga/_ver0.00/slave&lt;br /&gt;+ /fpga/_ver0.00/slave/slavespi.v&lt;br /&gt;+ /fpga/_ver0.00/slave/zx.h&lt;br /&gt;+ /fpga/_ver0.00/slave/zx_keys.txt&lt;br /&gt;+ /fpga/_ver0.00/vg93&lt;br /&gt;+ /fpga/_ver0.00/vg93/vg93.v&lt;br /&gt;+ /fpga/_ver0.00/video&lt;br /&gt;+ /fpga/_ver0.00/video/addresses.txt&lt;br /&gt;+ /fpga/_ver0.00/video/fetch.v&lt;br /&gt;+ /fpga/_ver0.00/video/synch.v&lt;br /&gt;+ /fpga/_ver0.00/video/syncv.v&lt;br /&gt;+ /fpga/_ver0.00/video/videoout.v&lt;br /&gt;+ /fpga/_ver0.00/video_modes.txt&lt;br /&gt;+ /fpga/_ver0.00/z80&lt;br /&gt;+ /fpga/_ver0.00/z80/zbus.v&lt;br /&gt;+ /fpga/_ver0.00/z80/zclock.v&lt;br /&gt;+ /fpga/_ver0.00/z80/zint.v&lt;br /&gt;+ /fpga/_ver0.00/z80/zmem.v&lt;br /&gt;+ /fpga/_ver0.00/z80/zports.v&lt;br /&gt;+ /fpga/_ver0.01&lt;br /&gt;+ /fpga/_ver0.01/common&lt;br /&gt;+ /fpga/_ver0.01/common/resetter.v&lt;br /&gt;+ /fpga/_ver0.01/common/spi2.v&lt;br /&gt;+ /fpga/_ver0.01/dram&lt;br /&gt;+ /fpga/_ver0.01/dram/arbiter.png&lt;br /&gt;+ /fpga/_ver0.01/dram/arbiter.v&lt;br /&gt;+ /fpga/_ver0.01/dram/cycles.txt&lt;br /&gt;+ /fpga/_ver0.01/dram/dram.v&lt;br /&gt;+ /fpga/_ver0.01/dram/test_compile.zip&lt;br /&gt;+ /fpga/_ver0.01/include&lt;br /&gt;+ /fpga/_ver0.01/include/tune.v&lt;br /&gt;+ /fpga/_ver0.01/quartus&lt;br /&gt;+ /fpga/_ver0.01/quartus/pentevo_0_01.qpf&lt;br /&gt;+ /fpga/_ver0.01/quartus/pentevo_0_01.qws&lt;br /&gt;+ /fpga/_ver0.01/quartus/top.qsf&lt;br /&gt;+ /fpga/_ver0.01/quartus/top.rbf&lt;br /&gt;+ /fpga/_ver0.01/quartus/top.sof&lt;br /&gt;+ /fpga/_ver0.01/README&lt;br /&gt;+ /fpga/_ver0.01/sim_cdv&lt;br /&gt;+ /fpga/_ver0.01/sim_cdv/a&lt;br /&gt;+ /fpga/_ver0.01/sim_cdv/b&lt;br /&gt;+ /fpga/_ver0.01/sim_cdv/tb.v&lt;br /&gt;+ /fpga/_ver0.01/sim_models&lt;br /&gt;+ /fpga/_ver0.01/sim_models/drammem.v&lt;br /&gt;+ /fpga/_ver0.01/sim_models/ram.v&lt;br /&gt;+ /fpga/_ver0.01/sim_models/rom.v&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80.vhd&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80a.vhd&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80_ALU.vhd&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80_MCode.vhd&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80_Pack.vhd&lt;br /&gt;+ /fpga/_ver0.01/sim_models/T80_Reg.vhd&lt;br /&gt;+ /fpga/_ver0.01/slave&lt;br /&gt;+ /fpga/_ver0.01/slave/slavespi.v&lt;br /&gt;+ /fpga/_ver0.01/slave/zx.h&lt;br /&gt;+ /fpga/_ver0.01/slave/zx_keys.txt&lt;br /&gt;+ /fpga/_ver0.01/texts&lt;br /&gt;+ /fpga/_ver0.01/texts/dram_access.txt&lt;br /&gt;+ /fpga/_ver0.01/texts/readme.txt&lt;br /&gt;+ /fpga/_ver0.01/texts/video_modes.txt&lt;br /&gt;+ /fpga/_ver0.01/top.v&lt;br /&gt;+ /fpga/_ver0.01/vg93&lt;br /&gt;+ /fpga/_ver0.01/vg93/vg93.v&lt;br /&gt;+ /fpga/_ver0.01/video&lt;br /&gt;+ /fpga/_ver0.01/video/addresses.txt&lt;br /&gt;+ /fpga/_ver0.01/video/fetch.v&lt;br /&gt;+ /fpga/_ver0.01/video/synch.v&lt;br /&gt;+ /fpga/_ver0.01/video/syncv.v&lt;br /&gt;+ /fpga/_ver0.01/video/videoout.v&lt;br /&gt;+ /fpga/_ver0.01/z80&lt;br /&gt;+ /fpga/_ver0.01/z80/zbus.v&lt;br /&gt;+ /fpga/_ver0.01/z80/zclock.v&lt;br /&gt;+ /fpga/_ver0.01/z80/zint.v&lt;br /&gt;+ /fpga/_ver0.01/z80/zmem.v&lt;br /&gt;+ /fpga/_ver0.01/z80/zports.v&lt;br /&gt;</description><link>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=4</link><guid>http://svn.zxevo.ru/revision.php?repname=pentevo&amp;path=%2Ffpga%2Fbase_trdemu%2Fnewirq%2Fcommon%2F&amp;isdir=1&amp;rev=4</guid></item>
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