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Rev Age Author Path Log message Diff
157 2018-12-24 17:59:02 lvd /trunk/cpld/rtl/ports.v merged newports into trunk  
116 2018-02-05 16:49:53 lvd /trunk/cpld/rtl/ports.v zxiznet: fixed years in rtl, spawned revC documentation  
84 2017-11-12 21:01:52 lvd /trunk/cpld/rtl/ports.v zxiznet: newclk branch merged back to trunk: tested verilog  
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ports.v trunk: added clocked filter, patched testbench to pass tests with that filter  
70 2017-09-18 00:15:06 dimkam /trunk/cpld/rtl/ports.v patch  
60 2013-10-03 10:12:41 lvd /trunk/cpld/rtl/ports.v zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/rtl/ports.v zxiznet: trying to fix glitches...  
48 2013-04-04 00:17:48 lvd /trunk/cpld/rtl/ports.v zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built  
32 2012-11-11 22:20:16 lvd /trunk/cpld/rtl/ports.v added port access to w5300 (HDL code, testbench, specs all updated)  
25 2012-11-03 23:41:28 lvd /trunk/cpld/rtl/ports.v added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ports.v updated verilog code according to new specs  
13 2012-10-13 19:38:42 lvd /trunk/cpld/rtl/ports.v initial verilog code and quartus project (not tested\!)