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71
2017-09-19 11:08:25
lvd
/trunk/cpld/
trunk: fixed obvious bug in tests
70
2017-09-18 00:15:06
dimkam
/trunk/cpld/
patch
62
2013-10-03 10:16:04
lvd
/trunk/cpld/
zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir
60
2013-10-03 10:12:41
lvd
/trunk/cpld/
zxiznet: dir structure
59
2013-10-03 10:09:34
lvd
/trunk/cpld/
zxiznet: trying to fix glitches...
58
2013-09-22 20:18:15
lvd
/trunk/cpld/
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill
52
2013-04-04 16:07:25
lvd
/trunk/cpld/
zxiznet: fixed nasty bug with not assigning pins and letting qva spread em randomly while changing RTL -- previous rev is therefore non-functional
48
2013-04-04 00:17:48
lvd
/trunk/cpld/
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built
40
2012-11-17 11:13:07
lvd
/trunk/cpld/
changed pins on CPLD for zxbus
35
2012-11-12 16:23:58
lvd
/trunk/cpld/
gate-level passed
34
2012-11-12 13:02:38
lvd
/trunk/cpld/
small update tp gate-level build script
33
2012-11-12 10:15:27
lvd
/trunk/cpld/
trying to add gate-level
32
2012-11-11 22:20:16
lvd
/trunk/cpld/
added port access to w5300 (HDL code, testbench, specs all updated)
31
2012-11-11 20:04:06
lvd
/trunk/cpld/
finished testbench for current cpld code
30
2012-11-11 16:03:39
lvd
/trunk/cpld/
basic tests OK
29
2012-11-11 10:20:58
lvd
/trunk/cpld/
started writing testbench tests
28
2012-11-07 06:09:01
lvd
/trunk/cpld/
updated tb a little
26
2012-11-04 15:13:22
lvd
/trunk/cpld/
finished USB-part, ZXBUS-part
25
2012-11-03 23:41:28
lvd
/trunk/cpld/
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs
23
2012-10-31 11:25:00
lvd
/trunk/cpld/
updated verilog code according to new specs
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