| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 152 |
2018-12-05 16:43:25 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
added branch branches/revC_newports with updated port structure for the ease of controlling w5300 via ports. not documented nor testbenched yet |
|
| 110 |
2018-02-04 21:42:37 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: revC: made pin test (see readme and top.v), compiled top.pof of main project, added empty epm config (read from empty device) |
|
| 109 |
2018-02-04 18:58:12 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: spawned simpe pin-test for epm3128 (DO NOT INSERT INTO ZXBUS\!\!\!) |
|
| 84 |
2017-11-12 21:01:52 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: newclk branch merged back to trunk: tested verilog |
|
| 72 |
2017-09-19 13:30:36 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
trunk: added clocked filter, patched testbench to pass tests with that filter |
|
| 70 |
2017-09-18 00:15:06 |
dimkam |
/branches/revC_newports/cpld/tests/top.v |
patch |
|
| 62 |
2013-10-03 10:16:04 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: trying to fix glitches... |
|
| 58 |
2013-09-22 20:18:15 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 23 |
2012-10-31 11:25:00 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
updated verilog code according to new specs |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
initial verilog code and quartus project (not tested\!) |
|
| 9 |
2012-10-10 20:05:06 |
lvd |
/branches/revC_newports/cpld/tests/top.v |
updated specs a bit, started cpld project |
|