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Rev Age Author Path Log message Diff
28 2012-11-07 06:09:01 lvd /branches/revC/cpld/rtl/ updated tb a little  
25 2012-11-03 23:41:28 lvd /branches/revC/cpld/rtl/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
23 2012-10-31 11:25:00 lvd /branches/revC/cpld/rtl/ updated verilog code according to new specs  
16 2012-10-22 01:35:08 lvd /branches/revC/cpld/rtl/ updated testbench a little  
15 2012-10-17 13:53:57 lvd /branches/revC/cpld/rtl/ updated testbench  
13 2012-10-13 19:38:42 lvd /branches/revC/cpld/rtl/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /branches/revC/cpld/rtl/ updated specs a bit, started cpld project  

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