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Rev Age Author Path Log message Diff Changes
35 2012-11-12 16:23:58 lvd /trunk/cpld/rtl/tb/ gate-level passed  
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
34 2012-11-12 13:02:38 lvd /trunk/cpld/rtl/tb/ small update tp gate-level build script  
/trunk/cpld/rtl/tb/cg
33 2012-11-12 10:15:27 lvd /trunk/cpld/ trying to add gate-level  
/trunk/cpld/rtl/tb/cg
/trunk/cpld/rtl/tb/testbench
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/files
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt
31 2012-11-11 20:04:06 lvd /trunk/cpld/ finished testbench for current cpld code  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/tb/tb.v
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
/trunk/cpld/rtl/tb/sc
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/zbus.v
29 2012-11-11 10:20:58 lvd /trunk/cpld/rtl/tb/ started writing testbench tests  
/trunk/cpld/rtl/tb/c.bat
/trunk/cpld/rtl/tb/d.bat
/trunk/cpld/rtl/tb/files
/trunk/cpld/rtl/tb/sg.bat
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/wave.do
28 2012-11-07 06:09:01 lvd /trunk/cpld/rtl/tb/ updated tb a little  
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
26 2012-11-04 15:13:22 lvd /trunk/ finished USB-part, ZXBUS-part  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/pcad/zxinet.sch
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
/trunk/pdfs/bc847.pdf
/trunk/pdfs/irlml6402.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
/trunk/pcad/libs/zxinet.lib
/trunk/pcad/zxinet.sch
/trunk/specs/specs.txt
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/top.v
22 2012-10-31 11:10:21 lvd /trunk/ changed specs: added BRDY read, added USB power control bits  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/specs/specs.txt
16 2012-10-22 01:35:08 lvd /trunk/cpld/rtl/tb/ updated testbench a little  
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/tb.v
15 2012-10-17 13:53:57 lvd /trunk/cpld/rtl/tb/ updated testbench  
/trunk/cpld/rtl/tb
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/d
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qpf
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project  
/trunk/cpld
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt

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