Top secrets sources NedoPC zxusbnet

Rev

Show changed files | Directory listing | RSS feed

Filtering Options

Rev Age Author Path Log message Diff
35 2012-11-12 16:23:58 lvd /branches/newclk/cpld/ gate-level passed  
34 2012-11-12 13:02:38 lvd /branches/newclk/cpld/ small update tp gate-level build script  
33 2012-11-12 10:15:27 lvd /branches/newclk/cpld/ trying to add gate-level  
32 2012-11-11 22:20:16 lvd /branches/newclk/cpld/ added port access to w5300 (HDL code, testbench, specs all updated)  
31 2012-11-11 20:04:06 lvd /branches/newclk/cpld/ finished testbench for current cpld code  
30 2012-11-11 16:03:39 lvd /branches/newclk/cpld/ basic tests OK  
29 2012-11-11 10:20:58 lvd /branches/newclk/cpld/ started writing testbench tests  
28 2012-11-07 06:09:01 lvd /branches/newclk/cpld/ updated tb a little  
26 2012-11-04 15:13:22 lvd /branches/newclk/cpld/ finished USB-part, ZXBUS-part  
25 2012-11-03 23:41:28 lvd /branches/newclk/cpld/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
23 2012-10-31 11:25:00 lvd /branches/newclk/cpld/ updated verilog code according to new specs  
22 2012-10-31 11:10:21 lvd /branches/newclk/cpld/ changed specs: added BRDY read, added USB power control bits  
16 2012-10-22 01:35:08 lvd /branches/newclk/cpld/ updated testbench a little  
15 2012-10-17 13:53:57 lvd /branches/newclk/cpld/ updated testbench  
13 2012-10-13 19:38:42 lvd /branches/newclk/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /branches/newclk/cpld/ updated specs a bit, started cpld project  

←Prev12Next→

Show All