| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 83 |
2017-11-12 19:28:10 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: sim debugged |
|
| 82 |
2017-11-12 01:47:02 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: sim debugging |
|
| 81 |
2017-11-01 17:06:25 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: changing design |
|
| 80 |
2017-10-31 16:00:04 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: changing design |
|
| 79 |
2017-10-31 15:20:04 |
lvd |
/branches/newclk/cpld/ |
zxiznet: making branch for new clocking/filtering system |
|
| 78 |
2017-10-30 15:05:39 |
lvd |
/branches/newclk/cpld/ |
zxiznet: comments added |
|
| 76 |
2017-09-28 15:00:24 |
lvd |
/branches/newclk/cpld/ |
zxiznet: TODO updated |
|
| 75 |
2017-09-26 17:40:44 |
lvd |
/branches/newclk/cpld/ |
zxiznet: revC TODO added |
|
| 74 |
2017-09-19 13:32:41 |
lvd |
/branches/newclk/cpld/ |
trunk: built .pof for the latest changed |
|
| 73 |
2017-09-19 13:31:13 |
lvd |
/branches/newclk/cpld/ |
trunk: fixed .qsf for building with CLOCKED_FILTER and NO_INTERRUPTS |
|
| 72 |
2017-09-19 13:30:36 |
lvd |
/branches/newclk/cpld/ |
trunk: added clocked filter, patched testbench to pass tests with that filter |
|
| 71 |
2017-09-19 11:08:25 |
lvd |
/branches/newclk/cpld/ |
trunk: fixed obvious bug in tests |
|
| 70 |
2017-09-18 00:15:06 |
dimkam |
/branches/newclk/cpld/ |
patch |
|
| 62 |
2013-10-03 10:16:04 |
lvd |
/branches/newclk/cpld/ |
zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/branches/newclk/cpld/ |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/branches/newclk/cpld/ |
zxiznet: trying to fix glitches... |
|
| 58 |
2013-09-22 20:18:15 |
lvd |
/branches/newclk/cpld/ |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
| 52 |
2013-04-04 16:07:25 |
lvd |
/branches/newclk/cpld/ |
zxiznet: fixed nasty bug with not assigning pins and letting qva spread em randomly while changing RTL -- previous rev is therefore non-functional |
|
| 48 |
2013-04-04 00:17:48 |
lvd |
/branches/newclk/cpld/ |
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built |
|
| 40 |
2012-11-17 11:13:07 |
lvd |
/branches/newclk/cpld/ |
changed pins on CPLD for zxbus |
|
| 35 |
2012-11-12 16:23:58 |
lvd |
/branches/newclk/cpld/ |
gate-level passed |
|
| 34 |
2012-11-12 13:02:38 |
lvd |
/branches/newclk/cpld/ |
small update tp gate-level build script |
|
| 33 |
2012-11-12 10:15:27 |
lvd |
/branches/newclk/cpld/ |
trying to add gate-level |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/branches/newclk/cpld/ |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 31 |
2012-11-11 20:04:06 |
lvd |
/branches/newclk/cpld/ |
finished testbench for current cpld code |
|
| 30 |
2012-11-11 16:03:39 |
lvd |
/branches/newclk/cpld/ |
basic tests OK |
|
| 29 |
2012-11-11 10:20:58 |
lvd |
/branches/newclk/cpld/ |
started writing testbench tests |
|
| 28 |
2012-11-07 06:09:01 |
lvd |
/branches/newclk/cpld/ |
updated tb a little |
|
| 26 |
2012-11-04 15:13:22 |
lvd |
/branches/newclk/cpld/ |
finished USB-part, ZXBUS-part |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/branches/newclk/cpld/ |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 23 |
2012-10-31 11:25:00 |
lvd |
/branches/newclk/cpld/ |
updated verilog code according to new specs |
|
| 22 |
2012-10-31 11:10:21 |
lvd |
/branches/newclk/cpld/ |
changed specs: added BRDY read, added USB power control bits |
|
| 16 |
2012-10-22 01:35:08 |
lvd |
/branches/newclk/cpld/ |
updated testbench a little |
|
| 15 |
2012-10-17 13:53:57 |
lvd |
/branches/newclk/cpld/ |
updated testbench |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/branches/newclk/cpld/ |
initial verilog code and quartus project (not tested\!) |
|
| 9 |
2012-10-10 20:05:06 |
lvd |
/branches/newclk/cpld/ |
updated specs a bit, started cpld project |
|