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Rev Age Author Path Log message Diff
23 2012-10-31 11:25:00 lvd /branches/clkfix/cpld/ updated verilog code according to new specs  
22 2012-10-31 11:10:21 lvd /branches/clkfix/cpld/ changed specs: added BRDY read, added USB power control bits  
16 2012-10-22 01:35:08 lvd /branches/clkfix/cpld/ updated testbench a little  
15 2012-10-17 13:53:57 lvd /branches/clkfix/cpld/ updated testbench  
13 2012-10-13 19:38:42 lvd /branches/clkfix/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /branches/clkfix/cpld/ updated specs a bit, started cpld project  

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