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Rev Age Author Path Log message Diff Changes
91 2017-12-12 23:36:00 lvd /branches/revC/pcad/revC/ zxiznet: routing revC  
/branches/revC/pcad/revC/zxinet.pcb
90 2017-12-07 19:59:44 lvd /branches/revC/pcad/revC/ zxiznet: unpoured (yet old) pcb  
/branches/revC/pcad/revC/zxinet.pcb
89 2017-12-07 02:50:32 lvd /branches/revC/pcad/revC/ zxiznet: last fixes to .sch  
/branches/revC/pcad/revC/zxinet.pcb
/branches/revC/pcad/revC/zxinet.sch
88 2017-12-07 02:36:48 lvd /branches/revC/pcad/revC/ zxiznet: added power selection for oscillators  
/branches/revC/pcad/revC/TODO
/branches/revC/pcad/revC/zxinet_tmp.sch
87 2017-11-14 00:50:46 lvd /branches/revC/pcad/revC/ zxiznet: changing schematics for revC  
/branches/revC/pcad/revC/TODO
/branches/revC/pcad/revC/zxinet_tmp.sch
86 2017-11-13 01:06:24 lvd /branches/revC/ zxiznet: changing schematics for revC  
/branches/revC/pcad/revC/README
/branches/revC/pcad/revC/zxinet_tmp.sch
/branches/revC/pdfs/clk_h53.pdf
/branches/revC/pdfs/clk_swo.pdf
/branches/revC/pcad/libs/zxinet.lib
/branches/revC/pcad/revC/TODO
85 2017-11-12 21:02:55 lvd /branches/revC/ zxiznet: new branch for revC schematics (branches/revC)  
/branches/revC
83 2017-11-12 19:28:10 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugged  
/branches/newclk/cpld/rtl/tb/sc
/branches/newclk/cpld/rtl/tb/ssz80.v
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/zbus.v
82 2017-11-12 01:47:02 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugging  
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/tb/wave.do
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
81 2017-11-01 17:06:25 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: changing design  
/branches/newclk/cpld/rtl/none.txt
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
80 2017-10-31 16:00:04 lvd /branches/newclk/cpld/ zxiznet: newclk: changing design  
/branches/newclk/cpld/quartus/top.qsf
/branches/newclk/cpld/rtl/none.txt
/branches/newclk/cpld/rtl/ports.v
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
79 2017-10-31 15:20:04 lvd /branches/newclk/ zxiznet: making branch for new clocking/filtering system  
/branches/newclk
69 2017-09-17 23:28:39 lvd /branches/clkfix/ test commit  
/branches/clkfix/TESTME
68 2014-10-26 21:51:58 lvd /branches/clkfix/cpld/quartus/ zxiznet: clkgen branch: successfull compilation of moved pinout  
/branches/clkfix/cpld/quartus/top.pof
/branches/clkfix/cpld/quartus/top.qsf
67 2014-10-26 19:18:34 lvd /branches/clkfix/cpld/ clkfix: removing sl811_rst_n pin  
/branches/clkfix/cpld/quartus/top.qsf
/branches/clkfix/cpld/rtl/ports.v
/branches/clkfix/cpld/rtl/top.v
66 2014-10-26 19:05:30 lvd /branches/clkfix/ Spawning new branch "clkfix" to try to fix glitches by adding extra clock to FPGA  
/branches/clkfix
65 2013-11-10 00:38:45 lvd /branches/glitch_fixes/cpld/rtl/ zxiznet: glitch_fixes branch: returned LCELLS parameter to 1  
/branches/glitch_fixes/cpld/rtl/top.v
63 2013-10-05 21:39:42 lvd /branches/glitch_fixes/cpld/ zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6  
/branches/glitch_fixes/cpld/quartus/top.pof
/branches/glitch_fixes/cpld/quartus/top.qsf
/branches/glitch_fixes/cpld/rtl/top.v
/branches/glitch_fixes/cpld/rtl/zbus.v
61 2013-10-03 10:13:46 lvd /branches/glitch_fixes/ branching glitch fixes code  
/branches/glitch_fixes
1 2012-10-03 10:29:21 lvd / added some old libs and PCBs from other projects  
/branches
/trunk
/trunk/pcad
/trunk/pcad/libs
/trunk/pcad/libs/NeoGS.lib
/trunk/pcad/libs/a6008mb2.lib
/trunk/pcad/libs/zxevo.lib
/trunk/pcad/old
/trunk/pcad/old/NeoGS.pcb

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