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Rev Age Author Path Log message Diff
565 2023-12-17 00:10:45 lvd /trunk/cpld/rtl/tb/tb.v tfmpro: fixed testbench for new mode[1:0] signal  
116 2017-12-03 23:23:15 lvd /trunk/cpld/rtl/tb/tb.v turbofmpro: full test seems to pass  
115 2017-12-03 02:24:51 chrv /trunk/cpld/rtl/tb/tb.v turbofmpro: initial test passes  
104 2017-11-15 14:56:59 lvd /trunk/cpld/rtl/tb/tb.v turbofmpro: started new RTL  
83 2017-01-19 11:03:52 lvd /trunk/cpld/rtl/tb/tb.v turbofmpro: updated testbench, simplified saa clock generator  
82 2017-01-11 17:45:59 lvd /trunk/cpld/rtl/tb/tb.v CPLD: started testbench, conf reg access fixed