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Rev Age Author Path Log message Diff
100 2013-05-20 11:04:23 lvd /fpga/current/tb/Makefile updated ports.inc, SD dma seems to work  
94 2013-05-10 23:43:19 lvd /fpga/current/tb/Makefile added 4 independent paging ports, written test for it, compiled design  
93 2013-05-10 14:20:05 lvd /fpga/current/tb/Makefile tested timer, built FPGA firmware with it  
91 2013-05-09 18:22:45 lvd /fpga/current/tb/Makefile testbench started to work, T80 int ack cycle is wrong