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Rev Age Author Path Log message Diff Changes
99 2013-05-20 02:24:50 lvd /fpga/current/ started TB for sd/mp3 dma  
/fpga/current/tb/mp3.v
/fpga/current/tb/sd.v
/fpga/current/dma/dma_mp3.v
/fpga/current/dma/dma_sd.v
/fpga/current/dma/dma_sequencer.v
/fpga/current/ports/ports.v
/fpga/current/sound/sound_main.v
/fpga/current/tb/c
/fpga/current/tb/tb.v
/fpga/current/top.v
94 2013-05-10 23:43:19 lvd / added 4 independent paging ports, written test for it, compiled design  
/fpga/current/tb/page_test.s
/docs/ports.inc
/fpga/current/memmap/memmap.v
/fpga/current/ports/ports.v
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
/fpga/current/tb/Makefile
/fpga/current/tb/rom_loader.s
/fpga/current/tb/tb.v
/fpga/current/tb/timer_test.s
/fpga/current/tb/wave.do
/fpga/current/top.v
88 2013-05-06 12:55:54 lvd /fpga/current/ fixed typos in added functionality, not tested yet  
/fpga/current/interrupts/interrupts.v
/fpga/current/interrupts/timer.v
/fpga/current/ports/ports.v
/fpga/current/quartus/main.qsf
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
87 2013-05-06 12:48:32 lvd /fpga/current/ started adding interrupt controller and timer  
/fpga/current/SPECS
/fpga/current/interrupts/timer.v
/fpga/current/interrupts/interrupts.v
/fpga/current/ports/ports.v
/fpga/current/top.v
64 2010-12-26 13:58:15 lvd /fpga/current/ trying to fix ngs rev C...  
/fpga/current/ports/ports.v
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
/fpga/current/zxbus/zxbus.v
62 2010-11-25 10:46:05 lvd /fpga/current/ fpga/current: added 4mb addressing  
/fpga/current/dma/dma_sequencer2.v
/fpga/current/dma/dma_access.v
/fpga/current/dma/dma_sd.v
/fpga/current/dma/dma_zx.v
/fpga/current/memmap/memmap.v
/fpga/current/ports/ports.v
/fpga/current/quartus/main.qsf
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
/fpga/current/top.v
61 2010-11-25 00:20:25 lvd /fpga/current/ started refucktoring code and adding new features to FPGA.
now fpga/current is head of development (not checked yet)		  
/fpga/current
/fpga/current/common/spi.v
/fpga/current/sound/sound_dac.v
/fpga/current/sound/sound_main.v
/fpga/current/top.v
/fpga/current/common/spi2.v
/fpga/current/dma/dma_zx2.v
/fpga/current/dma/dma_zx_old.v
/fpga/current/main.v
/fpga/current/quartus/main.qws
/fpga/current/sound/sound_dac2.v
/fpga/current/sound/sound_main2.v
/fpga/current/quartus/main.qsf
/fpga/current/readme.txt
6 2009-12-06 20:08:08 lvd / port GSCFG0, bit 7 - inversion of samples  
/fpga/fpgaF_dma2/quartus/main.rbf
/fpga/fpgaF_dma2/quartus/main.sof
/docs/ports.inc
/fpga/fpgaF_dma2/main.v
/fpga/fpgaF_dma2/ports/ports.v
/fpga/fpgaF_dma2/readme.txt
/fpga/fpgaF_dma2/sound/sound_main2.v
/fpga/fpgaF_dma2/sound/sound_mulacc.v
2 2009-11-21 21:52:10 lvd /fpga/fpgaF_dma2/ Just files, which all was forgotten in initial commit  
/fpga/fpgaF_dma2
/fpga/fpgaF_dma2/common
/fpga/fpgaF_dma2/common/mem512b.v
/fpga/fpgaF_dma2/common/resetter.v
/fpga/fpgaF_dma2/common/spi2.v
/fpga/fpgaF_dma2/common/spi2_modelled.png
/fpga/fpgaF_dma2/common/spi2_modelled.zip
/fpga/fpgaF_dma2/dma
/fpga/fpgaF_dma2/dma/dma_access.png
/fpga/fpgaF_dma2/dma/dma_access.v
/fpga/fpgaF_dma2/dma/dma_registers.txt
/fpga/fpgaF_dma2/dma/dma_sd.v
/fpga/fpgaF_dma2/dma/dma_sequencer.v
/fpga/fpgaF_dma2/dma/dma_sequencer2.v
/fpga/fpgaF_dma2/dma/dma_zx.v
/fpga/fpgaF_dma2/dma/dma_zx2.v
/fpga/fpgaF_dma2/dma/dma_zx_old.v
/fpga/fpgaF_dma2/dma/modelsim
/fpga/fpgaF_dma2/dma/modelsim/T80_MCode.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_Pack.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_Reg.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_RegX.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80a.vhd
/fpga/fpgaF_dma2/dma/modelsim/dbg1.do
/fpga/fpgaF_dma2/dma/modelsim/dma.cr.mti
/fpga/fpgaF_dma2/dma/modelsim/dma.mpf
/fpga/fpgaF_dma2/dma/modelsim/ram.v
/fpga/fpgaF_dma2/dma/modelsim/rom.v
/fpga/fpgaF_dma2/dma/modelsim/t80.vhd
/fpga/fpgaF_dma2/dma/modelsim/t80_alu.vhd
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.cr.mti
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.do
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.mpf
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.png
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.v
/fpga/fpgaF_dma2/dma/modelsim/tb_dma2.do
/fpga/fpgaF_dma2/dma/modelsim/tb_dma2.v
/fpga/fpgaF_dma2/dma/modelsim/wave.bmp
/fpga/fpgaF_dma2/dma/rr_arbiter_tb.v
/fpga/fpgaF_dma2/dma/sim
/fpga/fpgaF_dma2/dma/sim/d.do
/fpga/fpgaF_dma2/dma/sim/dma_tester.v
/fpga/fpgaF_dma2/dma/sim/rr_arbiter_tb.v
/fpga/fpgaF_dma2/dma/sim/tb_4way.v
/fpga/fpgaF_dma2/dma/sim/tb_dma1.v
/fpga/fpgaF_dma2/dma/sim/tb_dma2.v
/fpga/fpgaF_dma2/dma/sim/wave.do
/fpga/fpgaF_dma2/dma/sim_models
/fpga/fpgaF_dma2/dma/sim_models/T80_MCode.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_Pack.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_Reg.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_RegX.vhd_DONT_COMPILE_ME
/fpga/fpgaF_dma2/dma/sim_models/T80a.vhd
/fpga/fpgaF_dma2/dma/sim_models/ram.v
/fpga/fpgaF_dma2/dma/sim_models/rom.v
/fpga/fpgaF_dma2/dma/sim_models/t80.vhd
/fpga/fpgaF_dma2/dma/sim_models/t80_alu.vhd
/fpga/fpgaF_dma2/interrupts
/fpga/fpgaF_dma2/interrupts/interrupts.v
/fpga/fpgaF_dma2/main.v
/fpga/fpgaF_dma2/memmap
/fpga/fpgaF_dma2/memmap/memmap.v
/fpga/fpgaF_dma2/ports
/fpga/fpgaF_dma2/ports/ports.v
/fpga/fpgaF_dma2/quartus
/fpga/fpgaF_dma2/quartus/main.qpf
/fpga/fpgaF_dma2/quartus/main.qsf
/fpga/fpgaF_dma2/quartus/main.qws
/fpga/fpgaF_dma2/readme.txt
/fpga/fpgaF_dma2/sound
/fpga/fpgaF_dma2/sound/sound_dac2.v
/fpga/fpgaF_dma2/sound/sound_main2.v
/fpga/fpgaF_dma2/sound/sound_mulacc.v
/fpga/fpgaF_dma2/zxbus
/fpga/fpgaF_dma2/zxbus/zxbus.v