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Rev Age Author Path Log message Diff
37 2010-04-29 22:32:25 lvd /cpld/cpld5_buf/sim/tb.v gate-level passes test!  
34 2010-04-21 23:23:36 lvd /cpld/cpld5_buf/sim/tb.v next iteration...  
33 2010-04-20 11:33:19 lvd /cpld/cpld5_buf/sim/tb.v small correctons; gate level does not work yet  
30 2010-04-19 01:05:31 lvd /cpld/cpld5_buf/sim/tb.v testbench for cpld_buf finished and works with rtl, todo: run testbench on gate-level  
29 2010-04-16 00:57:41 lvd /cpld/cpld5_buf/sim/tb.v cpld tb up to fpga handover  
28 2010-04-15 01:04:37 lvd /cpld/cpld5_buf/sim/tb.v testbench update in progress...  
27 2010-04-14 10:28:14 lvd /cpld/cpld5_buf/sim/tb.v rommap test done for rtl  
26 2010-04-12 10:35:28 lvd /cpld/cpld5_buf/sim/tb.v same as below  
25 2010-04-09 23:26:34 lvd /cpld/cpld5_buf/sim/tb.v writing testbench for cpld_buf in progress  
24 2010-04-08 08:40:44 lvd /cpld/cpld5_buf/sim/tb.v clock switcher testbench  
23 2010-04-07 23:58:41 lvd /cpld/cpld5_buf/sim/tb.v Qua simulator suxx: using modelsim