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Rev Age Author Path Log message Diff Changes
66 2011-01-17 02:12:30 lvd /cpld/cpld5_buf/ cpld: fix by CHRV for no glitches  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
60 2010-11-23 12:13:09 lvd / rebuilt both cpld5 and fpgaF with Q72, updated a little NGS_prm  
/docs/NGS_prm/NGS_prm2.odt
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/docs/NGS_prm/NGS_prm.odt
/fpga/fpgaF_dma2/quartus/main.qsf
/fpga/fpgaF_dma2/quartus/main.rbf
/fpga/fpgaF_dma2/quartus/main.sof
58 2010-09-25 12:15:49 lvd / cpld5_buf: recompiled with slow slew rate; added ramtests (fast and slow, slow for many freqs, fast for 24 only)  
/fpga/ramtest_revC_fast
/fpga/ramtest_revC_fast/main.v
/fpga/ramtest_revC_fast/mem_tester
/fpga/ramtest_revC_fast/mem_tester/mem_tester.v
/fpga/ramtest_revC_fast/quartus
/fpga/ramtest_revC_fast/quartus/main.qpf
/fpga/ramtest_revC_fast/quartus/main.qsf
/fpga/ramtest_revC_fast/quartus/main.qws
/fpga/ramtest_revC_fast/quartus/main.rbf
/fpga/ramtest_revC_fast/quartus/main.sof
/fpga/ramtest_revC_fast/resetter
/fpga/ramtest_revC_fast/resetter/resetter.v
/fpga/ramtest_revC_fast/rnd_vec_gen
/fpga/ramtest_revC_fast/rnd_vec_gen/rnd_vec_gen.v
/fpga/ramtest_revC_fast/sim
/fpga/ramtest_revC_fast/sim/c
/fpga/ramtest_revC_fast/sim/d
/fpga/ramtest_revC_fast/sim/l
/fpga/ramtest_revC_fast/sim/s
/fpga/ramtest_revC_fast/sim/tb.v
/fpga/ramtest_revC_fast/sim/vlog.opt
/fpga/ramtest_revC_fast/sim/wave.do
/fpga/ramtest_revC_fast/sram_control
/fpga/ramtest_revC_fast/sram_control/sram_control.v
/fpga/ramtest_revC_slow
/fpga/ramtest_revC_slow/quartus/10mhz.sof
/fpga/ramtest_revC_slow/quartus/12mhz.sof
/fpga/ramtest_revC_slow/quartus/20mhz.sof
/fpga/ramtest_revC_slow/quartus/24mhz.sof
/fpga/ramtest_revC
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
49 2010-07-26 08:49:05 lvd /cpld/cpld5_buf/ updated pinout of CPLD for current .sch  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
40 2010-05-15 13:07:59 chrv /cpld/cpld5_buf/ pin assigment (equal sch)  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
30 2010-04-19 01:05:31 lvd /cpld/cpld5_buf/ testbench for cpld_buf finished and works with rtl, todo: run testbench on gate-level  
/cpld/cpld5_buf/sim/gate/max_atoms.v
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/cpld/cpld5_buf/sim/tb.v
25 2010-04-09 23:26:34 lvd /cpld/cpld5_buf/ writing testbench for cpld_buf in progress  
/cpld/cpld5_buf/sim/GS_3032.txt
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/GS_cpld.v
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
/cpld/cpld5_buf/test1.cvwf
22 2010-04-04 12:38:56 lvd /cpld/cpld5_buf/ testing of cpld_buf begins  
/cpld/cpld5_buf/test1.cvwf
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/GS_cpld.v
20 2010-03-21 20:51:29 lvd / revC schematics updated, cpld5_buf updated for rev.C board: no checking, no pinmapping yet  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.v
/pcad/revC/NeoGS.sch
/pcad/revC/none.txt
17 2010-03-18 01:18:08 lvd / start of big changes in cpld5_buf and revC schematics \(probably\)  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qpf
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/GS_cpld.v
/pcad/revC/74_74LCX245.pdf
/pcad/revC/none.txt
/cpld/cpld5_buf/GS_3032.fit.summary
/cpld/cpld5_buf/GS_3032.map.summary
/cpld/cpld5_buf/GS_3032.qpf
/cpld/cpld5_buf/GS_3032.qsf
/cpld/cpld5_buf/GS_3032.tan.summary
/cpld/cpld5_buf/GS_3032.v
/pcad/revC/NeoGS.sch
/pcad/revC/todo.txt