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122 2014-05-18 15:36:48 lvd /cpld/cpld6_revC_onlyclock/ ngs: added onlyclock version of CPLD for rev.C board  
/cpld/cpld6_revC_onlyclock
/cpld/cpld6_revC_onlyclock/sim
/cpld/cpld6_revC_onlyclock/test1.cvwf
/cpld/cpld6_revC_onlyclock/GS_cpld.pof
/cpld/cpld6_revC_onlyclock/GS_cpld.v
66 2011-01-17 02:12:30 lvd /cpld/cpld5_buf/ cpld: fix by CHRV for no glitches  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
60 2010-11-23 12:13:09 lvd / rebuilt both cpld5 and fpgaF with Q72, updated a little NGS_prm  
/docs/NGS_prm/NGS_prm2.odt
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/docs/NGS_prm/NGS_prm.odt
/fpga/fpgaF_dma2/quartus/main.qsf
/fpga/fpgaF_dma2/quartus/main.rbf
/fpga/fpgaF_dma2/quartus/main.sof
58 2010-09-25 12:15:49 lvd / cpld5_buf: recompiled with slow slew rate; added ramtests (fast and slow, slow for many freqs, fast for 24 only)  
/fpga/ramtest_revC_fast
/fpga/ramtest_revC_fast/main.v
/fpga/ramtest_revC_fast/mem_tester
/fpga/ramtest_revC_fast/mem_tester/mem_tester.v
/fpga/ramtest_revC_fast/quartus
/fpga/ramtest_revC_fast/quartus/main.qpf
/fpga/ramtest_revC_fast/quartus/main.qsf
/fpga/ramtest_revC_fast/quartus/main.qws
/fpga/ramtest_revC_fast/quartus/main.rbf
/fpga/ramtest_revC_fast/quartus/main.sof
/fpga/ramtest_revC_fast/resetter
/fpga/ramtest_revC_fast/resetter/resetter.v
/fpga/ramtest_revC_fast/rnd_vec_gen
/fpga/ramtest_revC_fast/rnd_vec_gen/rnd_vec_gen.v
/fpga/ramtest_revC_fast/sim
/fpga/ramtest_revC_fast/sim/c
/fpga/ramtest_revC_fast/sim/d
/fpga/ramtest_revC_fast/sim/l
/fpga/ramtest_revC_fast/sim/s
/fpga/ramtest_revC_fast/sim/tb.v
/fpga/ramtest_revC_fast/sim/vlog.opt
/fpga/ramtest_revC_fast/sim/wave.do
/fpga/ramtest_revC_fast/sram_control
/fpga/ramtest_revC_fast/sram_control/sram_control.v
/fpga/ramtest_revC_slow
/fpga/ramtest_revC_slow/quartus/10mhz.sof
/fpga/ramtest_revC_slow/quartus/12mhz.sof
/fpga/ramtest_revC_slow/quartus/20mhz.sof
/fpga/ramtest_revC_slow/quartus/24mhz.sof
/fpga/ramtest_revC
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
49 2010-07-26 08:49:05 lvd /cpld/cpld5_buf/ updated pinout of CPLD for current .sch  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
40 2010-05-15 13:07:59 chrv /cpld/cpld5_buf/ pin assigment (equal sch)  
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
37 2010-04-29 22:32:25 lvd /cpld/cpld5_buf/sim/ gate-level passes test!  
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
34 2010-04-21 23:23:36 lvd /cpld/cpld5_buf/ next iteration...  
/cpld/cpld5_buf/GS_cpld.v
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
33 2010-04-20 11:33:19 lvd /cpld/cpld5_buf/sim/ small correctons; gate level does not work yet  
/cpld/cpld5_buf/sim/s.bat
/cpld/cpld5_buf/sim/tb.v
32 2010-04-19 10:00:38 lvd /cpld/cpld5_buf/sim/ small update to filelist in cpld_buf/sim  
/cpld/cpld5_buf/sim/vlog-gate.opt
/cpld/cpld5_buf/sim/cg.bat
31 2010-04-19 01:24:11 lvd /cpld/cpld5_buf/sim/ small update to previous  
/cpld/cpld5_buf/sim/cg
/cpld/cpld5_buf/sim/s
30 2010-04-19 01:05:31 lvd /cpld/cpld5_buf/ testbench for cpld_buf finished and works with rtl, todo: run testbench on gate-level  
/cpld/cpld5_buf/sim/gate/max_atoms.v
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/cpld/cpld5_buf/sim/tb.v
29 2010-04-16 00:57:41 lvd /cpld/cpld5_buf/sim/ cpld tb up to fpga handover  
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
28 2010-04-15 01:04:37 lvd /cpld/cpld5_buf/ testbench update in progress...  
/cpld/cpld5_buf/GS_cpld.v
/cpld/cpld5_buf/sim/tb.v
27 2010-04-14 10:28:14 lvd / rommap test done for rtl  
/cpld/cpld5_buf/sim/tb.v
/pcad/revC/NeoGS.sch
26 2010-04-12 10:35:28 lvd /cpld/cpld5_buf/sim/ same as below  
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
25 2010-04-09 23:26:34 lvd /cpld/cpld5_buf/ writing testbench for cpld_buf in progress  
/cpld/cpld5_buf/sim/GS_3032.txt
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/GS_cpld.v
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/wave.do
/cpld/cpld5_buf/test1.cvwf
24 2010-04-08 08:40:44 lvd /cpld/cpld5_buf/sim/ clock switcher testbench  
/cpld/cpld5_buf/sim/clocker_sim.v
/cpld/cpld5_buf/sim/tb.v
23 2010-04-07 23:58:41 lvd /cpld/cpld5_buf/sim/ Qua simulator suxx: using modelsim  
/cpld/cpld5_buf/sim
/cpld/cpld5_buf/sim/c
/cpld/cpld5_buf/sim/c.bat
/cpld/cpld5_buf/sim/cg
/cpld/cpld5_buf/sim/cg.bat
/cpld/cpld5_buf/sim/clocker_sim.v
/cpld/cpld5_buf/sim/d
/cpld/cpld5_buf/sim/d.bat
/cpld/cpld5_buf/sim/gate
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/cpld/cpld5_buf/sim/l
/cpld/cpld5_buf/sim/l.bat
/cpld/cpld5_buf/sim/s
/cpld/cpld5_buf/sim/s.bat
/cpld/cpld5_buf/sim/tb.v
/cpld/cpld5_buf/sim/vlog.opt
/cpld/cpld5_buf/sim/wave.do
22 2010-04-04 12:38:56 lvd /cpld/cpld5_buf/ testing of cpld_buf begins  
/cpld/cpld5_buf/test1.cvwf
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/GS_cpld.v

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