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918 2020-11-29 18:39:06 lvd /fpga/sdload/ pentevo: initial sdload config (copied from baseconf)  
/fpga/sdload
896 2020-11-14 20:24:33 lvd / pentevo: changing repo structure  
/cfgs
/cfgs/standalone_baseconf
/cfgs/standalone_baseconf/trunk
/cfgs/standalone_baseconf/trunk/README
/fpga/baseconf
/fpga/baseconf/trunk
/fpga/baseconf/trunk/GPL
/fpga/baseconf/trunk/TODO
/fpga/baseconf/trunk/ULAPLUS
/fpga/baseconf/trunk/common
/fpga/baseconf/trunk/dram
/fpga/baseconf/trunk/include
/fpga/baseconf/trunk/mem
/fpga/baseconf/trunk/quartus
/fpga/baseconf/trunk/sim_models
/fpga/baseconf/trunk/sim_top
/fpga/baseconf/trunk/slave
/fpga/baseconf/trunk/sound
/fpga/baseconf/trunk/spihub
/fpga/baseconf/trunk/texts
/fpga/baseconf/trunk/top.v
/fpga/baseconf/trunk/vg93
/fpga/baseconf/trunk/video
/fpga/baseconf/trunk/z80
/fpga/trdemu/trunk
/fpga/trdemu/trunk/TODO
/fpga/trdemu/trunk/ULAPLUS
/fpga/trdemu/trunk/common
/fpga/trdemu/trunk/dram
/fpga/trdemu/trunk/include
/fpga/trdemu/trunk/mem
/fpga/trdemu/trunk/quartus
/fpga/trdemu/trunk/sim_models
/fpga/trdemu/trunk/sim_top
/fpga/trdemu/trunk/slave
/fpga/trdemu/trunk/sound
/fpga/trdemu/trunk/spihub
/fpga/trdemu/trunk/texts
/fpga/trdemu/trunk/top.v
/fpga/trdemu/trunk/vg93
/fpga/trdemu/trunk/video
/fpga/trdemu/trunk/z80
/fpga/trdemu/trunk/zxevo_base_configuration.odt
/fpga/trdemu/trunk/zxevo_fw.bin
684 2015-01-13 17:53:16 lvd / updated srcs for ULA emulation  
/fpga/current/sim_models/cmosemu.v
/fpga/current/sim_top/c48k
/fpga/current/sim_top/ccontend
/fpga/current/sim_top/dw5.bin
/avr/current/main.h
/avr/current/zx.c
/fpga/current/mem/atm_pager.v
/fpga/current/sim_models/T80.vhd
/fpga/current/sim_models/T80_Pack.vhd
/fpga/current/sim_models/T80a.vhd
/fpga/current/sim_top/Makefile
/fpga/current/sim_top/sc
/fpga/current/sim_top/tb_top.v
/fpga/current/sim_top/vlog.opt
/fpga/current/sim_top/wave.do
/fpga/current/top.v
/fpga/current/video/video_palframe.v
/fpga/current/video/video_sync_h.v
/fpga/current/video/video_sync_v.v
/fpga/current/video/video_top.v
/fpga/current/video/video_vga_sync_h.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zmem.v
/fpga/current/z80/zports.v
/fpga/current/z80/zwait.v
668 2014-07-29 10:01:19 lvd / pentevo: added ulaplus, fixed NMI to RAM (DimkaM request)  
/fpga/current/GPL
/fpga/current/ULAPLUS
/fpga/current/FIXME
/fpga/current/README
/fpga/current/TODO
/fpga/current/vga
/avr/current/default/core.hex
/avr/current/default/zxevo_fw.bin
/fpga/current/common/resetter.v
/fpga/current/dram/arbiter.v
/fpga/current/dram/dram.v
/fpga/current/include/tune.v
/fpga/current/mem/atm_pager.v
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/slave/slavespi.v
/fpga/current/sound/sound.v
/fpga/current/spihub/spi2.v
/fpga/current/spihub/spihub.v
/fpga/current/top.v
/fpga/current/vg93/fapch_counter.v
/fpga/current/vg93/fapch_zek.v
/fpga/current/vg93/vg93.v
/fpga/current/video/video_addrgen.v
/fpga/current/video/video_fetch.v
/fpga/current/video/video_modedecode.v
/fpga/current/video/video_outmux.v
/fpga/current/video/video_palframe.v
/fpga/current/video/video_render.v
/fpga/current/video/video_sync_h.v
/fpga/current/video/video_sync_v.v
/fpga/current/video/video_top.v
/fpga/current/video/video_vga_double.v
/fpga/current/video/video_vga_sync_h.v
/fpga/current/z80/zbreak.v
/fpga/current/z80/zbus.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zdos.v
/fpga/current/z80/zint.v
/fpga/current/z80/zkbdmus.v
/fpga/current/z80/zmem.v
/fpga/current/z80/znmi.v
/fpga/current/z80/zports.v
/fpga/current/z80/zwait.v
467 2011-07-14 23:08:27 lvd /fpga/current/ merged z14 with trunk  
/fpga/current/sim_top/c35
/fpga/current/sim_top/c7
/fpga/current
/fpga/current/TODO
/fpga/current/dram/arbiter.v
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/sim_models/T80a.vhd
/fpga/current/sim_top/Makefile
/fpga/current/sim_top/pixer.v
/fpga/current/sim_top/tb_top.v
/fpga/current/sim_top/wave.do
/fpga/current/top.v
/fpga/current/video/video_addrgen.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zmem.v
/fpga/current/z80/zports.v
425 2011-06-05 17:12:18 lvd /fpga/current/ atm_nmi merging with current  
/fpga/current/sim_top/Makefile
/fpga/current/sim_top/pixer.v
/fpga/current/sim_top/sc
/fpga/current/sim_top/sg
/fpga/current/sim_top/sndpix.c
/fpga/current/sim_top/sndpix.h
/fpga/current/sim_top/viewer.c
/fpga/current/sim_top/zxevo_rom.v
/fpga/current/z80/znmi.v
/fpga/current/sim_top/l
/fpga/current/sim_top/s
/fpga/current
/fpga/current/common/resetter.v
/fpga/current/dram/dram.v
/fpga/current/mem/atm_pager.v
/fpga/current/quartus/top.qsf
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/sim_top/c
/fpga/current/sim_top/d
/fpga/current/sim_top/rom_top.v
/fpga/current/sim_top/tb_top.v
/fpga/current/sim_top/vlog.opt
/fpga/current/sim_top/wave.do
/fpga/current/slave/slavespi.v
/fpga/current/top.v
/fpga/current/video/video_fontrom.v
/fpga/current/video/video_palframe.v
/fpga/current/video/video_sync_h.v
/fpga/current/video/video_top.v
/fpga/current/z80/none.txt
/fpga/current/z80/zclock.v
/fpga/current/z80/zint.v
/fpga/current/z80/zports.v
/fpga/current/z80/zwait.v
200 2010-04-30 01:29:13 lvd /fpga/current/ merged atm_mem to current  
/fpga/current/FIXME
/fpga/current/mem
/fpga/current/sim_top/c
/fpga/current/sim_top/d
/fpga/current/sim_top/l
/fpga/current/sim_top/s
/fpga/current/sim_top/test.rom
/fpga/current/sim_top/testrom.v
/fpga/current/sim_top/zxevo_rom.v
/fpga/current/z80/zdos.v
/fpga/current/quartus/top_fix_ide_maybe.zip
/fpga/current/slave/zx.h
/fpga/current
/fpga/current/dram/dram.v
/fpga/current/quartus/top.qsf
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/sim_models/drammem.v
/fpga/current/sim_top/rom_top.v
/fpga/current/sim_top/tb_top.v
/fpga/current/sim_top/vlog.opt
/fpga/current/sim_top/wave.do
/fpga/current/slave/slavespi.v
/fpga/current/top.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zint.v
/fpga/current/z80/zkbdmus.v
/fpga/current/z80/zmem.v
/fpga/current/z80/zports.v
/fpga/current/z80/zwait.v
41 2009-12-11 00:31:20 lvd /fpga/current/ continuing...  
/fpga/current/quartus/top.qsf
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/sim_top/wave.do
/fpga/current/top.v
/fpga/current/z80/zclock.v
40 2009-12-08 00:12:49 lvd /fpga/current/ starting redesign from two clocks (zports.v) to single clock (fclk) and zpos-zneg strobes (zclock.v). May be broken now, not tested in hardware  
/fpga/current/sim_top/wave.do
/fpga/current/slave/slavespi.v
/fpga/current/top.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zports.v
30 2009-12-03 00:09:55 lvd /fpga/current/ complete testbench. does not work.  
/fpga/current/dram/arbiter.v
/fpga/current/dram/dram.v
/fpga/current/include/tune.v
/fpga/current/quartus/pentevo_0_01.qws
/fpga/current/sim_cdv/tb.v
/fpga/current/sim_models/ram.v
/fpga/current/sim_models/rom.v
/fpga/current/slave/slavespi.v
/fpga/current/top.v
/fpga/current/vg93/vg93.v
/fpga/current/video/fetch.v
/fpga/current/video/synch.v
/fpga/current/video/syncv.v
/fpga/current/video/videoout.v
/fpga/current/z80/zbus.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zint.v
/fpga/current/z80/zmem.v
/fpga/current/z80/zports.v
4 2009-11-21 21:06:56 lvd / initial commit of FPGA files  
/fpga
/fpga/_ver0.00
/fpga/_ver0.00/common
/fpga/_ver0.00/common/resetter.v
/fpga/_ver0.00/common/spi2.v
/fpga/_ver0.00/dram
/fpga/_ver0.00/dram/arbiter.png
/fpga/_ver0.00/dram/arbiter.v
/fpga/_ver0.00/dram/cycles.txt
/fpga/_ver0.00/dram/dram.v
/fpga/_ver0.00/dram/test_compile
/fpga/_ver0.00/dram/test_compile/arbiter.cvwf
/fpga/_ver0.00/dram/test_compile/arbiter.qsf
/fpga/_ver0.00/dram/test_compile/arbiter_description.txt
/fpga/_ver0.00/dram/test_compile/test_compile.qpf
/fpga/_ver0.00/dram/test_compile/test_compile.qws
/fpga/_ver0.00/dram/test_compile/test_compile.v
/fpga/_ver0.00/dram_access.txt
/fpga/_ver0.00/include
/fpga/_ver0.00/include/tune.v
/fpga/_ver0.00/keyboard
/fpga/_ver0.00/main.v
/fpga/_ver0.00/readme.txt
/fpga/_ver0.00/sim_cdv
/fpga/_ver0.00/sim_cdv/a
/fpga/_ver0.00/sim_cdv/b
/fpga/_ver0.00/sim_cdv/sim_cdv.cr.mti
/fpga/_ver0.00/sim_cdv/sim_cdv.mpf
/fpga/_ver0.00/sim_cdv/tb.v
/fpga/_ver0.00/sim_models
/fpga/_ver0.00/sim_models/T80.vhd
/fpga/_ver0.00/sim_models/T80_ALU.vhd
/fpga/_ver0.00/sim_models/T80_MCode.vhd
/fpga/_ver0.00/sim_models/T80_Pack.vhd
/fpga/_ver0.00/sim_models/T80_Reg.vhd
/fpga/_ver0.00/sim_models/T80a.vhd
/fpga/_ver0.00/sim_models/drammem.v
/fpga/_ver0.00/sim_models/ram.v
/fpga/_ver0.00/sim_models/rom.v
/fpga/_ver0.00/slave
/fpga/_ver0.00/slave/slavespi.v
/fpga/_ver0.00/slave/zx.h
/fpga/_ver0.00/slave/zx_keys.txt
/fpga/_ver0.00/vg93
/fpga/_ver0.00/vg93/vg93.v
/fpga/_ver0.00/video
/fpga/_ver0.00/video/addresses.txt
/fpga/_ver0.00/video/fetch.v
/fpga/_ver0.00/video/synch.v
/fpga/_ver0.00/video/syncv.v
/fpga/_ver0.00/video/videoout.v
/fpga/_ver0.00/video_modes.txt
/fpga/_ver0.00/z80
/fpga/_ver0.00/z80/zbus.v
/fpga/_ver0.00/z80/zclock.v
/fpga/_ver0.00/z80/zint.v
/fpga/_ver0.00/z80/zmem.v
/fpga/_ver0.00/z80/zports.v
/fpga/_ver0.01
/fpga/_ver0.01/README
/fpga/_ver0.01/common
/fpga/_ver0.01/common/resetter.v
/fpga/_ver0.01/common/spi2.v
/fpga/_ver0.01/dram
/fpga/_ver0.01/dram/arbiter.png
/fpga/_ver0.01/dram/arbiter.v
/fpga/_ver0.01/dram/cycles.txt
/fpga/_ver0.01/dram/dram.v
/fpga/_ver0.01/dram/test_compile.zip
/fpga/_ver0.01/include
/fpga/_ver0.01/include/tune.v
/fpga/_ver0.01/quartus
/fpga/_ver0.01/quartus/pentevo_0_01.qpf
/fpga/_ver0.01/quartus/pentevo_0_01.qws
/fpga/_ver0.01/quartus/top.qsf
/fpga/_ver0.01/quartus/top.rbf
/fpga/_ver0.01/quartus/top.sof
/fpga/_ver0.01/sim_cdv
/fpga/_ver0.01/sim_cdv/a
/fpga/_ver0.01/sim_cdv/b
/fpga/_ver0.01/sim_cdv/tb.v
/fpga/_ver0.01/sim_models
/fpga/_ver0.01/sim_models/T80.vhd
/fpga/_ver0.01/sim_models/T80_ALU.vhd
/fpga/_ver0.01/sim_models/T80_MCode.vhd
/fpga/_ver0.01/sim_models/T80_Pack.vhd
/fpga/_ver0.01/sim_models/T80_Reg.vhd
/fpga/_ver0.01/sim_models/T80a.vhd
/fpga/_ver0.01/sim_models/drammem.v
/fpga/_ver0.01/sim_models/ram.v
/fpga/_ver0.01/sim_models/rom.v
/fpga/_ver0.01/slave
/fpga/_ver0.01/slave/slavespi.v
/fpga/_ver0.01/slave/zx.h
/fpga/_ver0.01/slave/zx_keys.txt
/fpga/_ver0.01/texts
/fpga/_ver0.01/texts/dram_access.txt
/fpga/_ver0.01/texts/readme.txt
/fpga/_ver0.01/texts/video_modes.txt
/fpga/_ver0.01/top.v
/fpga/_ver0.01/vg93
/fpga/_ver0.01/vg93/vg93.v
/fpga/_ver0.01/video
/fpga/_ver0.01/video/addresses.txt
/fpga/_ver0.01/video/fetch.v
/fpga/_ver0.01/video/synch.v
/fpga/_ver0.01/video/syncv.v
/fpga/_ver0.01/video/videoout.v
/fpga/_ver0.01/z80
/fpga/_ver0.01/z80/zbus.v
/fpga/_ver0.01/z80/zclock.v
/fpga/_ver0.01/z80/zint.v
/fpga/_ver0.01/z80/zmem.v
/fpga/_ver0.01/z80/zports.v
/fpga/current
/fpga/current/README
/fpga/current/common
/fpga/current/common/resetter.v
/fpga/current/common/spi2.v
/fpga/current/dram
/fpga/current/dram/arbiter.png
/fpga/current/dram/arbiter.v
/fpga/current/dram/cycles.txt
/fpga/current/dram/dram.v
/fpga/current/dram/test_compile.zip
/fpga/current/include
/fpga/current/include/tune.v
/fpga/current/quartus
/fpga/current/quartus/pentevo_0_01.qpf
/fpga/current/quartus/pentevo_0_01.qws
/fpga/current/quartus/top.qsf
/fpga/current/quartus/top.rbf
/fpga/current/quartus/top.sof
/fpga/current/quartus/top_fix_ide_maybe.zip
/fpga/current/sim_cdv
/fpga/current/sim_cdv/a
/fpga/current/sim_cdv/b
/fpga/current/sim_cdv/tb.v
/fpga/current/sim_models
/fpga/current/sim_models/T80.vhd
/fpga/current/sim_models/T80_ALU.vhd
/fpga/current/sim_models/T80_MCode.vhd
/fpga/current/sim_models/T80_Pack.vhd
/fpga/current/sim_models/T80_Reg.vhd
/fpga/current/sim_models/T80a.vhd
/fpga/current/sim_models/drammem.v
/fpga/current/sim_models/ram.v
/fpga/current/sim_models/rom.v
/fpga/current/slave
/fpga/current/slave/slavespi.v
/fpga/current/slave/zx.h
/fpga/current/slave/zx_keys.txt
/fpga/current/texts
/fpga/current/texts/dram_access.txt
/fpga/current/texts/readme.txt
/fpga/current/texts/video_modes.txt
/fpga/current/top.v
/fpga/current/vg93
/fpga/current/vg93/vg93.v
/fpga/current/video
/fpga/current/video/addresses.txt
/fpga/current/video/fetch.v
/fpga/current/video/synch.v
/fpga/current/video/syncv.v
/fpga/current/video/videoout.v
/fpga/current/z80
/fpga/current/z80/zbus.v
/fpga/current/z80/zclock.v
/fpga/current/z80/zint.v
/fpga/current/z80/zmem.v
/fpga/current/z80/zports.v
/fpga/tests
/fpga/tests/test_dram
/fpga/tests/test_dram/dram.v
/fpga/tests/test_dram/dram_control.v
/fpga/tests/test_dram/main.qsf
/fpga/tests/test_dram/main.rbf
/fpga/tests/test_dram/main.sof
/fpga/tests/test_dram/main.v
/fpga/tests/test_dram/main_.v
/fpga/tests/test_dram/mem_tester.v
/fpga/tests/test_dram/resetter.v
/fpga/tests/test_dram/rnd_vec_gen.v
/fpga/tests/test_dram/sram_control.v
/fpga/tests/test_dram/stable.sof
/fpga/tests/test_dram/test_dram.qpf
/fpga/tests/test_dram/test_dram.qws
/fpga/tests/test_ledblink
/fpga/tests/test_ledblink/dram.v
/fpga/tests/test_ledblink/main.qsf
/fpga/tests/test_ledblink/main.v
/fpga/tests/test_ledblink/stable.sof
/fpga/tests/test_ledblink/test_ledblink.qpf
/fpga/tests/test_ledblink/test_ledblink.qws
/file1st