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Rev	Age	Author	Path	Log message	Diff	Changes
918	2020-11-29 18:39:06	lvd	/fpga/sdload/	pentevo: initial sdload config (copied from baseconf)		/fpga/sdload
896	2020-11-14 20:24:33	lvd	/	pentevo: changing repo structure		/cfgs /cfgs/standalone_baseconf /cfgs/standalone_baseconf/trunk /cfgs/standalone_baseconf/trunk/README /fpga/baseconf /fpga/baseconf/trunk /fpga/baseconf/trunk/GPL /fpga/baseconf/trunk/TODO /fpga/baseconf/trunk/ULAPLUS /fpga/baseconf/trunk/common /fpga/baseconf/trunk/dram /fpga/baseconf/trunk/include /fpga/baseconf/trunk/mem /fpga/baseconf/trunk/quartus /fpga/baseconf/trunk/sim_models /fpga/baseconf/trunk/sim_top /fpga/baseconf/trunk/slave /fpga/baseconf/trunk/sound /fpga/baseconf/trunk/spihub /fpga/baseconf/trunk/texts /fpga/baseconf/trunk/top.v /fpga/baseconf/trunk/vg93 /fpga/baseconf/trunk/video /fpga/baseconf/trunk/z80 /fpga/trdemu/trunk /fpga/trdemu/trunk/TODO /fpga/trdemu/trunk/ULAPLUS /fpga/trdemu/trunk/common /fpga/trdemu/trunk/dram /fpga/trdemu/trunk/include /fpga/trdemu/trunk/mem /fpga/trdemu/trunk/quartus /fpga/trdemu/trunk/sim_models /fpga/trdemu/trunk/sim_top /fpga/trdemu/trunk/slave /fpga/trdemu/trunk/sound /fpga/trdemu/trunk/spihub /fpga/trdemu/trunk/texts /fpga/trdemu/trunk/top.v /fpga/trdemu/trunk/vg93 /fpga/trdemu/trunk/video /fpga/trdemu/trunk/z80 /fpga/trdemu/trunk/zxevo_base_configuration.odt /fpga/trdemu/trunk/zxevo_fw.bin
511	2011-12-27 12:49:28	lvd	/fpga/current/sim_top/	changed simulation evnironment to support windows-based old modelsim, added signals to wave		/fpga/current/sim_top/c.bat /fpga/current/sim_top/d.bat /fpga/current/sim_top/pixer.v /fpga/current/sim_top/s.bat /fpga/current/sim_top/tb_top.v /fpga/current/sim_top/wave.do
29	2009-12-03 00:09:33	lvd	/fpga/current/sim_top/	complete testbench. does not work.		/fpga/current/sim_top /fpga/current/sim_top/c.bat /fpga/current/sim_top/d.bat /fpga/current/sim_top/l.bat /fpga/current/sim_top/s.bat /fpga/current/sim_top/tb_top.v /fpga/current/sim_top/vcom.opt /fpga/current/sim_top/vlog.opt /fpga/current/sim_top/wave.do