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ngs
?pathlinks? – Rev 85
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85
2013-05-05 22:51:42
lvd
/fpga/
moved older fpga sources to obsolete\/ directory
/fpga/obsolete
/fpga/obsolete/fpgaC_release
/fpga/obsolete/fpgaD_release
/fpga/obsolete/fpgaE_dma
/fpga/obsolete/fpgaF_dma2
/fpga/obsolete/ramtest_05112008
/fpga/obsolete/ramtest_revC_fast
/fpga/obsolete/ramtest_revC_slow
/fpga/fpgaC_release
/fpga/fpgaD_release
/fpga/fpgaE_dma
/fpga/fpgaF_dma2
/fpga/ramtest_05112008
/fpga/ramtest_revC_fast
/fpga/ramtest_revC_slow
6
2009-12-06 20:08:08
lvd
/
port GSCFG0, bit 7 - inversion of samples
/fpga/fpgaF_dma2/quartus/main.rbf
/fpga/fpgaF_dma2/quartus/main.sof
/docs/ports.inc
/fpga/fpgaF_dma2/main.v
/fpga/fpgaF_dma2/ports/ports.v
/fpga/fpgaF_dma2/readme.txt
/fpga/fpgaF_dma2/sound/sound_main2.v
/fpga/fpgaF_dma2/sound/sound_mulacc.v
2
2009-11-21 21:52:10
lvd
/fpga/fpgaF_dma2/
Just files, which all was forgotten in initial commit
/fpga/fpgaF_dma2
/fpga/fpgaF_dma2/common
/fpga/fpgaF_dma2/common/mem512b.v
/fpga/fpgaF_dma2/common/resetter.v
/fpga/fpgaF_dma2/common/spi2.v
/fpga/fpgaF_dma2/common/spi2_modelled.png
/fpga/fpgaF_dma2/common/spi2_modelled.zip
/fpga/fpgaF_dma2/dma
/fpga/fpgaF_dma2/dma/dma_access.png
/fpga/fpgaF_dma2/dma/dma_access.v
/fpga/fpgaF_dma2/dma/dma_registers.txt
/fpga/fpgaF_dma2/dma/dma_sd.v
/fpga/fpgaF_dma2/dma/dma_sequencer.v
/fpga/fpgaF_dma2/dma/dma_sequencer2.v
/fpga/fpgaF_dma2/dma/dma_zx.v
/fpga/fpgaF_dma2/dma/dma_zx2.v
/fpga/fpgaF_dma2/dma/dma_zx_old.v
/fpga/fpgaF_dma2/dma/modelsim
/fpga/fpgaF_dma2/dma/modelsim/T80_MCode.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_Pack.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_Reg.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80_RegX.vhd
/fpga/fpgaF_dma2/dma/modelsim/T80a.vhd
/fpga/fpgaF_dma2/dma/modelsim/dbg1.do
/fpga/fpgaF_dma2/dma/modelsim/dma.cr.mti
/fpga/fpgaF_dma2/dma/modelsim/dma.mpf
/fpga/fpgaF_dma2/dma/modelsim/ram.v
/fpga/fpgaF_dma2/dma/modelsim/rom.v
/fpga/fpgaF_dma2/dma/modelsim/t80.vhd
/fpga/fpgaF_dma2/dma/modelsim/t80_alu.vhd
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.cr.mti
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.do
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.mpf
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.png
/fpga/fpgaF_dma2/dma/modelsim/tb_dma1.v
/fpga/fpgaF_dma2/dma/modelsim/tb_dma2.do
/fpga/fpgaF_dma2/dma/modelsim/tb_dma2.v
/fpga/fpgaF_dma2/dma/modelsim/wave.bmp
/fpga/fpgaF_dma2/dma/rr_arbiter_tb.v
/fpga/fpgaF_dma2/dma/sim
/fpga/fpgaF_dma2/dma/sim/d.do
/fpga/fpgaF_dma2/dma/sim/dma_tester.v
/fpga/fpgaF_dma2/dma/sim/rr_arbiter_tb.v
/fpga/fpgaF_dma2/dma/sim/tb_4way.v
/fpga/fpgaF_dma2/dma/sim/tb_dma1.v
/fpga/fpgaF_dma2/dma/sim/tb_dma2.v
/fpga/fpgaF_dma2/dma/sim/wave.do
/fpga/fpgaF_dma2/dma/sim_models
/fpga/fpgaF_dma2/dma/sim_models/T80_MCode.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_Pack.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_Reg.vhd
/fpga/fpgaF_dma2/dma/sim_models/T80_RegX.vhd_DONT_COMPILE_ME
/fpga/fpgaF_dma2/dma/sim_models/T80a.vhd
/fpga/fpgaF_dma2/dma/sim_models/ram.v
/fpga/fpgaF_dma2/dma/sim_models/rom.v
/fpga/fpgaF_dma2/dma/sim_models/t80.vhd
/fpga/fpgaF_dma2/dma/sim_models/t80_alu.vhd
/fpga/fpgaF_dma2/interrupts
/fpga/fpgaF_dma2/interrupts/interrupts.v
/fpga/fpgaF_dma2/main.v
/fpga/fpgaF_dma2/memmap
/fpga/fpgaF_dma2/memmap/memmap.v
/fpga/fpgaF_dma2/ports
/fpga/fpgaF_dma2/ports/ports.v
/fpga/fpgaF_dma2/quartus
/fpga/fpgaF_dma2/quartus/main.qpf
/fpga/fpgaF_dma2/quartus/main.qsf
/fpga/fpgaF_dma2/quartus/main.qws
/fpga/fpgaF_dma2/readme.txt
/fpga/fpgaF_dma2/sound
/fpga/fpgaF_dma2/sound/sound_dac2.v
/fpga/fpgaF_dma2/sound/sound_main2.v
/fpga/fpgaF_dma2/sound/sound_mulacc.v
/fpga/fpgaF_dma2/zxbus
/fpga/fpgaF_dma2/zxbus/zxbus.v