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Rev Age Author Path Log message Diff Changes
94 2013-05-10 23:43:19 lvd / added 4 independent paging ports, written test for it, compiled design  
/fpga/current/tb/page_test.s
/docs/ports.inc
/fpga/current/memmap/memmap.v
/fpga/current/ports/ports.v
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
/fpga/current/tb/Makefile
/fpga/current/tb/rom_loader.s
/fpga/current/tb/tb.v
/fpga/current/tb/timer_test.s
/fpga/current/tb/wave.do
/fpga/current/top.v
93 2013-05-10 14:20:05 lvd /fpga/current/ tested timer, built FPGA firmware with it  
/fpga/current/tb/s
/fpga/current/tb/timer_test.s
/fpga/current/SPECS
/fpga/current/interrupts/interrupts.v
/fpga/current/quartus/main.qsf
/fpga/current/quartus/main.rbf
/fpga/current/quartus/main.sof
/fpga/current/tb/Makefile
/fpga/current/tb/rom_loader.s
/fpga/current/tb/wave.do
92 2013-05-09 20:51:14 lvd /fpga/current/ used tv80 instead of T80  
/fpga/current/tb/wave.do
/fpga/current/tb/z80/t80_latest.tar.gz
/fpga/current/tb/z80/tv80_alu.v
/fpga/current/tb/z80/tv80_core.v
/fpga/current/tb/z80/tv80_latest.tar.gz
/fpga/current/tb/z80/tv80_mcode.v
/fpga/current/tb/z80/tv80_reg.v
/fpga/current/tb/z80/tv80n.v
/fpga/current/tb/z80/tv80s.v
/fpga/current/interrupts/interrupts.v
/fpga/current/tb/c
/fpga/current/tb/rom_loader.s
/fpga/current/tb/z80/z80.v
91 2013-05-09 18:22:45 lvd / testbench started to work, T80 int ack cycle is wrong  
/fpga/current/tb/Makefile
/fpga/current/tb/rom.v
/fpga/current/tb/rom_loader.s
/docs/ports.inc
/fpga/current/interrupts/timer.v
/fpga/current/quartus/main.qsf
/fpga/current/sound/sound_main.v
/fpga/current/tb/c
/fpga/current/tb/ram.v
/fpga/current/tb/tb.v
/fpga/current/tb/z80/z80.v
/fpga/current/top.v
/fpga/current/zxbus/zxbus.v