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Rev	Age	Author	Path	Log message	Diff	Changes
100	2013-05-20 11:04:23	lvd	/	updated ports.inc, SD dma seems to work		/fpga/current/tb/sdmp3_test.s /docs/ports.inc /fpga/current/tb/Makefile /fpga/current/tb/c /fpga/current/tb/mp3.v /fpga/current/tb/sd.v /fpga/current/tb/tb.v /fpga/current/tb/wave.do /fpga/current/tb/z80/z80.v /fpga/current/top.v
94	2013-05-10 23:43:19	lvd	/	added 4 independent paging ports, written test for it, compiled design		/fpga/current/tb/page_test.s /docs/ports.inc /fpga/current/memmap/memmap.v /fpga/current/ports/ports.v /fpga/current/quartus/main.rbf /fpga/current/quartus/main.sof /fpga/current/tb/Makefile /fpga/current/tb/rom_loader.s /fpga/current/tb/tb.v /fpga/current/tb/timer_test.s /fpga/current/tb/wave.do /fpga/current/top.v
93	2013-05-10 14:20:05	lvd	/fpga/current/	tested timer, built FPGA firmware with it		/fpga/current/tb/s /fpga/current/tb/timer_test.s /fpga/current/SPECS /fpga/current/interrupts/interrupts.v /fpga/current/quartus/main.qsf /fpga/current/quartus/main.rbf /fpga/current/quartus/main.sof /fpga/current/tb/Makefile /fpga/current/tb/rom_loader.s /fpga/current/tb/wave.do
91	2013-05-09 18:22:45	lvd	/	testbench started to work, T80 int ack cycle is wrong		/fpga/current/tb/Makefile /fpga/current/tb/rom.v /fpga/current/tb/rom_loader.s /docs/ports.inc /fpga/current/interrupts/timer.v /fpga/current/quartus/main.qsf /fpga/current/sound/sound_main.v /fpga/current/tb/c /fpga/current/tb/ram.v /fpga/current/tb/tb.v /fpga/current/tb/z80/z80.v /fpga/current/top.v /fpga/current/zxbus/zxbus.v