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?pathlinks? – Rev 121

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Rev	Age	Author	Path	Log message	Diff	Changes
121	2014-05-16 22:49:04	lvd	/fpga/	pgmflash: altera part seems finished:		/fpga/pgmflash/quartus/main.sof /fpga/current/quartus/main.qsf /fpga/pgmflash/SPECS /fpga/pgmflash/quartus/main.qsf /fpga/pgmflash/rom/rom.v /fpga/pgmflash/tb/tb.v /fpga/pgmflash/top.v /fpga/pgmflash/zxbus/zxbus.v
101	2013-05-21 02:11:16	lvd	/fpga/current/	sd-mp3 dmas seem to work, full test to be written		/fpga/current/tb/Makefile.win /fpga/current/dma/dma_mp3.v /fpga/current/quartus/main.qsf /fpga/current/tb/c /fpga/current/tb/sdmp3_test.s /fpga/current/tb/wave.do /fpga/current/top.v
93	2013-05-10 14:20:05	lvd	/fpga/current/	tested timer, built FPGA firmware with it		/fpga/current/tb/s /fpga/current/tb/timer_test.s /fpga/current/SPECS /fpga/current/interrupts/interrupts.v /fpga/current/quartus/main.qsf /fpga/current/quartus/main.rbf /fpga/current/quartus/main.sof /fpga/current/tb/Makefile /fpga/current/tb/rom_loader.s /fpga/current/tb/wave.do
91	2013-05-09 18:22:45	lvd	/	testbench started to work, T80 int ack cycle is wrong		/fpga/current/tb/Makefile /fpga/current/tb/rom.v /fpga/current/tb/rom_loader.s /docs/ports.inc /fpga/current/interrupts/timer.v /fpga/current/quartus/main.qsf /fpga/current/sound/sound_main.v /fpga/current/tb/c /fpga/current/tb/ram.v /fpga/current/tb/tb.v /fpga/current/tb/z80/z80.v /fpga/current/top.v /fpga/current/zxbus/zxbus.v
88	2013-05-06 12:55:54	lvd	/fpga/current/	fixed typos in added functionality, not tested yet		/fpga/current/interrupts/interrupts.v /fpga/current/interrupts/timer.v /fpga/current/ports/ports.v /fpga/current/quartus/main.qsf /fpga/current/quartus/main.rbf /fpga/current/quartus/main.sof
62	2010-11-25 10:46:05	lvd	/fpga/current/	fpga/current: added 4mb addressing		/fpga/current/dma/dma_sequencer2.v /fpga/current/dma/dma_access.v /fpga/current/dma/dma_sd.v /fpga/current/dma/dma_zx.v /fpga/current/memmap/memmap.v /fpga/current/ports/ports.v /fpga/current/quartus/main.qsf /fpga/current/quartus/main.rbf /fpga/current/quartus/main.sof /fpga/current/top.v
61	2010-11-25 00:20:25	lvd	/fpga/current/	started refucktoring code and adding new features to FPGA. now fpga/current is head of development (not checked yet)		/fpga/current /fpga/current/common/spi.v /fpga/current/sound/sound_dac.v /fpga/current/sound/sound_main.v /fpga/current/top.v /fpga/current/common/spi2.v /fpga/current/dma/dma_zx2.v /fpga/current/dma/dma_zx_old.v /fpga/current/main.v /fpga/current/quartus/main.qws /fpga/current/sound/sound_dac2.v /fpga/current/sound/sound_main2.v /fpga/current/quartus/main.qsf /fpga/current/readme.txt
60	2010-11-23 12:13:09	lvd	/	rebuilt both cpld5 and fpgaF with Q72, updated a little NGS_prm		/docs/NGS_prm/NGS_prm2.odt /cpld/cpld5_buf/GS_cpld.pof /cpld/cpld5_buf/GS_cpld.qsf /cpld/cpld5_buf/sim/gate/GS_cpld.vo /cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo /docs/NGS_prm/NGS_prm.odt /fpga/fpgaF_dma2/quartus/main.qsf /fpga/fpgaF_dma2/quartus/main.rbf /fpga/fpgaF_dma2/quartus/main.sof
2	2009-11-21 21:52:10	lvd	/fpga/fpgaF_dma2/	Just files, which all was forgotten in initial commit		/fpga/fpgaF_dma2 /fpga/fpgaF_dma2/common /fpga/fpgaF_dma2/common/mem512b.v /fpga/fpgaF_dma2/common/resetter.v /fpga/fpgaF_dma2/common/spi2.v /fpga/fpgaF_dma2/common/spi2_modelled.png /fpga/fpgaF_dma2/common/spi2_modelled.zip /fpga/fpgaF_dma2/dma /fpga/fpgaF_dma2/dma/dma_access.png /fpga/fpgaF_dma2/dma/dma_access.v /fpga/fpgaF_dma2/dma/dma_registers.txt /fpga/fpgaF_dma2/dma/dma_sd.v /fpga/fpgaF_dma2/dma/dma_sequencer.v /fpga/fpgaF_dma2/dma/dma_sequencer2.v /fpga/fpgaF_dma2/dma/dma_zx.v /fpga/fpgaF_dma2/dma/dma_zx2.v /fpga/fpgaF_dma2/dma/dma_zx_old.v /fpga/fpgaF_dma2/dma/modelsim /fpga/fpgaF_dma2/dma/modelsim/T80_MCode.vhd /fpga/fpgaF_dma2/dma/modelsim/T80_Pack.vhd /fpga/fpgaF_dma2/dma/modelsim/T80_Reg.vhd /fpga/fpgaF_dma2/dma/modelsim/T80_RegX.vhd /fpga/fpgaF_dma2/dma/modelsim/T80a.vhd /fpga/fpgaF_dma2/dma/modelsim/dbg1.do /fpga/fpgaF_dma2/dma/modelsim/dma.cr.mti /fpga/fpgaF_dma2/dma/modelsim/dma.mpf /fpga/fpgaF_dma2/dma/modelsim/ram.v /fpga/fpgaF_dma2/dma/modelsim/rom.v /fpga/fpgaF_dma2/dma/modelsim/t80.vhd /fpga/fpgaF_dma2/dma/modelsim/t80_alu.vhd /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.cr.mti /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.do /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.mpf /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.png /fpga/fpgaF_dma2/dma/modelsim/tb_dma1.v /fpga/fpgaF_dma2/dma/modelsim/tb_dma2.do /fpga/fpgaF_dma2/dma/modelsim/tb_dma2.v /fpga/fpgaF_dma2/dma/modelsim/wave.bmp /fpga/fpgaF_dma2/dma/rr_arbiter_tb.v /fpga/fpgaF_dma2/dma/sim /fpga/fpgaF_dma2/dma/sim/d.do /fpga/fpgaF_dma2/dma/sim/dma_tester.v /fpga/fpgaF_dma2/dma/sim/rr_arbiter_tb.v /fpga/fpgaF_dma2/dma/sim/tb_4way.v /fpga/fpgaF_dma2/dma/sim/tb_dma1.v /fpga/fpgaF_dma2/dma/sim/tb_dma2.v /fpga/fpgaF_dma2/dma/sim/wave.do /fpga/fpgaF_dma2/dma/sim_models /fpga/fpgaF_dma2/dma/sim_models/T80_MCode.vhd /fpga/fpgaF_dma2/dma/sim_models/T80_Pack.vhd /fpga/fpgaF_dma2/dma/sim_models/T80_Reg.vhd /fpga/fpgaF_dma2/dma/sim_models/T80_RegX.vhd_DONT_COMPILE_ME /fpga/fpgaF_dma2/dma/sim_models/T80a.vhd /fpga/fpgaF_dma2/dma/sim_models/ram.v /fpga/fpgaF_dma2/dma/sim_models/rom.v /fpga/fpgaF_dma2/dma/sim_models/t80.vhd /fpga/fpgaF_dma2/dma/sim_models/t80_alu.vhd /fpga/fpgaF_dma2/interrupts /fpga/fpgaF_dma2/interrupts/interrupts.v /fpga/fpgaF_dma2/main.v /fpga/fpgaF_dma2/memmap /fpga/fpgaF_dma2/memmap/memmap.v /fpga/fpgaF_dma2/ports /fpga/fpgaF_dma2/ports/ports.v /fpga/fpgaF_dma2/quartus /fpga/fpgaF_dma2/quartus/main.qpf /fpga/fpgaF_dma2/quartus/main.qsf /fpga/fpgaF_dma2/quartus/main.qws /fpga/fpgaF_dma2/readme.txt /fpga/fpgaF_dma2/sound /fpga/fpgaF_dma2/sound/sound_dac2.v /fpga/fpgaF_dma2/sound/sound_main2.v /fpga/fpgaF_dma2/sound/sound_mulacc.v /fpga/fpgaF_dma2/zxbus /fpga/fpgaF_dma2/zxbus/zxbus.v