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Rev Age Author Path Log message Diff
152 2018-12-05 16:43:25 lvd /branches/revC_newports/ added branch branches/revC_newports with updated port structure for the ease of controlling w5300 via ports. not documented nor testbenched yet  
110 2018-02-04 21:42:37 lvd /trunk/ zxiznet: revC: made pin test (see readme and top.v), compiled top.pof of main project, added empty epm config (read from empty device)  
109 2018-02-04 18:58:12 lvd /trunk/cpld/tests/ zxiznet: spawned simpe pin-test for epm3128 (DO NOT INSERT INTO ZXBUS\!\!\!)  
84 2017-11-12 21:01:52 lvd /trunk/ zxiznet: newclk branch merged back to trunk: tested verilog  
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
70 2017-09-18 00:15:06 dimkam /trunk/cpld/ patch  
62 2013-10-03 10:16:04 lvd /trunk/cpld/ zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project