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Rev Age Author Path Log message Diff
188 2020-02-24 17:16:20 lvd /branches/p2666fix_smaller_brd_bwr/cpld/ p2666dfix_smaller_brd_bwr: done  
186 2020-02-24 16:56:32 lvd /branches/p2666fix_smaller_brd_bwr/ making some branches for p2666 fixes  
134 2018-03-05 18:26:20 lvd /trunk/cpld/ zxiznet: updated fix for <look prev commit>  
133 2018-03-05 17:33:21 lvd /trunk/cpld/ zxiznet: proposed fix for data setup violation in memmaped wiznet memtest  
132 2018-03-04 03:00:51 lvd /trunk/cpld/ zxiznet: fix for bad memmapped w5300 reads when extra bytes appeared or some disappearing. still read glitches at 14mhz, when some zero bits of read byte turn to 1 (also memmaped w5300)  
121 2018-02-12 01:18:17 lvd /trunk/cpld/ zxiznet: fixing for 14mhz: sl811 seems to work also, but fix overall is BAAAD. Will do lOOOng tests though  
120 2018-02-09 03:07:46 lvd /trunk/cpld/ zxiznet: fixing for 14mhz: w5300 works OK, sl811 always fails (any freq)  
116 2018-02-05 16:49:53 lvd /trunk/ zxiznet: fixed years in rtl, spawned revC documentation  
84 2017-11-12 21:01:52 lvd /trunk/ zxiznet: newclk branch merged back to trunk: tested verilog  
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
70 2017-09-18 00:15:06 dimkam /trunk/cpld/ patch  
62 2013-10-03 10:16:04 lvd /trunk/cpld/ zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project