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Rev Age Author Path Log message Diff Changes
83 2017-11-12 19:28:10 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugged  
/branches/newclk/cpld/rtl/tb/sc
/branches/newclk/cpld/rtl/tb/ssz80.v
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/zbus.v
82 2017-11-12 01:47:02 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugging  
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/tb/wave.do
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
81 2017-11-01 17:06:25 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: changing design  
/branches/newclk/cpld/rtl/none.txt
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
80 2017-10-31 16:00:04 lvd /branches/newclk/cpld/ zxiznet: newclk: changing design  
/branches/newclk/cpld/quartus/top.qsf
/branches/newclk/cpld/rtl/none.txt
/branches/newclk/cpld/rtl/ports.v
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
79 2017-10-31 15:20:04 lvd /branches/newclk/ zxiznet: making branch for new clocking/filtering system  
/branches/newclk
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
70 2017-09-18 00:15:06 dimkam /trunk/cpld/ patch  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
62 2013-10-03 10:16:04 lvd /trunk/cpld/ zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
/trunk/cpld/fix
/trunk/cpld/fix/quartus
/trunk/cpld/fix/rtl
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix/quartus/top.pof
/trunk/cpld/fix/quartus/top.qsf
/trunk/cpld/fix/rtl/top.v
/trunk/cpld/fix/rtl/zbus.v
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
/trunk/cpld/rtl/tb/sc
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/zbus.v
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
/trunk/pdfs/bc847.pdf
/trunk/pdfs/irlml6402.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
/trunk/pcad/libs/zxinet.lib
/trunk/pcad/zxinet.sch
/trunk/specs/specs.txt
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qpf
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project  
/trunk/cpld
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt