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Rev Age Author Path Log message Diff
83 2017-11-12 19:28:10 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugged  
82 2017-11-12 01:47:02 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugging  
81 2017-11-01 17:06:25 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: changing design  
80 2017-10-31 16:00:04 lvd /branches/newclk/cpld/ zxiznet: newclk: changing design  
79 2017-10-31 15:20:04 lvd /branches/newclk/ zxiznet: making branch for new clocking/filtering system  
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
70 2017-09-18 00:15:06 dimkam /trunk/cpld/ patch  
62 2013-10-03 10:16:04 lvd /trunk/cpld/ zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project