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83 2017-11-12 19:28:10 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugged  
/branches/newclk/cpld/rtl/tb/sc
/branches/newclk/cpld/rtl/tb/ssz80.v
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/zbus.v
82 2017-11-12 01:47:02 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugging  
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/tb/wave.do
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
81 2017-11-01 17:06:25 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: changing design  
/branches/newclk/cpld/rtl/none.txt
/branches/newclk/cpld/rtl/tb/tb.v
/branches/newclk/cpld/rtl/top.v
/branches/newclk/cpld/rtl/zbus.v
79 2017-10-31 15:20:04 lvd /branches/newclk/ zxiznet: making branch for new clocking/filtering system  
/branches/newclk
76 2017-09-28 15:00:24 lvd /trunk/ zxiznet: TODO updated  
/trunk/cpld/rtl/tb/tb.v
/trunk/pcad/revC/TODO
75 2017-09-26 17:40:44 lvd /trunk/ zxiznet: revC TODO added  
/trunk/pcad/revC
/trunk/pcad/revC/TODO
/trunk/cpld/rtl/tb/tb.v
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
71 2017-09-19 11:08:25 lvd /trunk/cpld/rtl/tb/ trunk: fixed obvious bug in tests  
/trunk/cpld/rtl/tb/tb.v
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
/trunk/cpld/fix
/trunk/cpld/fix/quartus
/trunk/cpld/fix/rtl
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix/quartus/top.pof
/trunk/cpld/fix/quartus/top.qsf
/trunk/cpld/fix/rtl/top.v
/trunk/cpld/fix/rtl/zbus.v
35 2012-11-12 16:23:58 lvd /trunk/cpld/rtl/tb/ gate-level passed  
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
33 2012-11-12 10:15:27 lvd /trunk/cpld/ trying to add gate-level  
/trunk/cpld/rtl/tb/cg
/trunk/cpld/rtl/tb/testbench
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/files
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt
31 2012-11-11 20:04:06 lvd /trunk/cpld/ finished testbench for current cpld code  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/tb/tb.v
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
/trunk/cpld/rtl/tb/sc
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/zbus.v
29 2012-11-11 10:20:58 lvd /trunk/cpld/rtl/tb/ started writing testbench tests  
/trunk/cpld/rtl/tb/c.bat
/trunk/cpld/rtl/tb/d.bat
/trunk/cpld/rtl/tb/files
/trunk/cpld/rtl/tb/sg.bat
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/wave.do
28 2012-11-07 06:09:01 lvd /trunk/cpld/rtl/tb/ updated tb a little  
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/w5300.v
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/top.v
16 2012-10-22 01:35:08 lvd /trunk/cpld/rtl/tb/ updated testbench a little  
/trunk/cpld/rtl/tb/sl811.v
/trunk/cpld/rtl/tb/w5300.v
/trunk/cpld/rtl/tb/tb.v
15 2012-10-17 13:53:57 lvd /trunk/cpld/rtl/tb/ updated testbench  
/trunk/cpld/rtl/tb
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/d
/trunk/cpld/rtl/tb/sg
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do