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Rev Age Author Path Log message Diff
83 2017-11-12 19:28:10 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugged  
82 2017-11-12 01:47:02 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: sim debugging  
81 2017-11-01 17:06:25 lvd /branches/newclk/cpld/rtl/ zxiznet: newclk: changing design  
79 2017-10-31 15:20:04 lvd /branches/newclk/ zxiznet: making branch for new clocking/filtering system  
76 2017-09-28 15:00:24 lvd /trunk/ zxiznet: TODO updated  
75 2017-09-26 17:40:44 lvd /trunk/ zxiznet: revC TODO added  
72 2017-09-19 13:30:36 lvd /trunk/cpld/rtl/ trunk: added clocked filter, patched testbench to pass tests with that filter  
71 2017-09-19 11:08:25 lvd /trunk/cpld/rtl/tb/ trunk: fixed obvious bug in tests  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
35 2012-11-12 16:23:58 lvd /trunk/cpld/rtl/tb/ gate-level passed  
33 2012-11-12 10:15:27 lvd /trunk/cpld/ trying to add gate-level  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
31 2012-11-11 20:04:06 lvd /trunk/cpld/ finished testbench for current cpld code  
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
29 2012-11-11 10:20:58 lvd /trunk/cpld/rtl/tb/ started writing testbench tests  
28 2012-11-07 06:09:01 lvd /trunk/cpld/rtl/tb/ updated tb a little  
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
16 2012-10-22 01:35:08 lvd /trunk/cpld/rtl/tb/ updated testbench a little  
15 2012-10-17 13:53:57 lvd /trunk/cpld/rtl/tb/ updated testbench