| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 65 |
2013-11-10 00:38:45 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
zxiznet: glitch_fixes branch: returned LCELLS parameter to 1 |
|
| 63 |
2013-10-05 21:39:42 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6 |
|
| 61 |
2013-10-03 10:13:46 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
branching glitch fixes code |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
zxiznet: trying to fix glitches... |
|
| 58 |
2013-09-22 20:18:15 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 23 |
2012-10-31 11:25:00 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
updated verilog code according to new specs |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
initial verilog code and quartus project (not tested\!) |
|
| 9 |
2012-10-10 20:05:06 |
lvd |
/branches/glitch_fixes/cpld/rtl/top.v |
updated specs a bit, started cpld project |
|