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Rev Age Author Path Log message Diff Changes
65 2013-11-10 00:38:45 lvd /branches/glitch_fixes/cpld/rtl/ zxiznet: glitch_fixes branch: returned LCELLS parameter to 1  
/branches/glitch_fixes/cpld/rtl/top.v
63 2013-10-05 21:39:42 lvd /branches/glitch_fixes/cpld/ zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6  
/branches/glitch_fixes/cpld/quartus/top.pof
/branches/glitch_fixes/cpld/quartus/top.qsf
/branches/glitch_fixes/cpld/rtl/top.v
/branches/glitch_fixes/cpld/rtl/zbus.v
61 2013-10-03 10:13:46 lvd /branches/glitch_fixes/ branching glitch fixes code  
/branches/glitch_fixes
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
/trunk/cpld/fix
/trunk/cpld/fix/quartus
/trunk/cpld/fix/rtl
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix/quartus/top.pof
/trunk/cpld/fix/quartus/top.qsf
/trunk/cpld/fix/rtl/top.v
/trunk/cpld/fix/rtl/zbus.v
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/tb/wave.do
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
/trunk/pdfs/bc847.pdf
/trunk/pdfs/irlml6402.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
/trunk/pcad/libs/zxinet.lib
/trunk/pcad/zxinet.sch
/trunk/specs/specs.txt
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/tb/tb.v
/trunk/cpld/rtl/top.v
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qpf
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project  
/trunk/cpld
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v
/trunk/specs/specs.txt