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Rev Age Author Path Log message Diff Changes
63 2013-10-05 21:39:42 lvd /branches/glitch_fixes/cpld/ zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6  
/branches/glitch_fixes/cpld/quartus/top.pof
/branches/glitch_fixes/cpld/quartus/top.qsf
/branches/glitch_fixes/cpld/rtl/top.v
/branches/glitch_fixes/cpld/rtl/zbus.v
61 2013-10-03 10:13:46 lvd /branches/glitch_fixes/ branching glitch fixes code  
/branches/glitch_fixes
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
/trunk/cpld/fix
/trunk/cpld/fix/quartus
/trunk/cpld/fix/rtl
/trunk/cpld/quartus
/trunk/cpld/rtl
/trunk/cpld/fix/quartus/top.pof
/trunk/cpld/fix/quartus/top.qsf
/trunk/cpld/fix/rtl/top.v
/trunk/cpld/fix/rtl/zbus.v
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
52 2013-04-04 16:07:25 lvd /trunk/cpld/quartus/ zxiznet: fixed nasty bug with not assigning pins and letting qva spread em randomly while changing RTL -- previous rev is therefore non-functional  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
48 2013-04-04 00:17:48 lvd /trunk/ zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/specs/specs.txt
40 2012-11-17 11:13:07 lvd /trunk/ changed pins on CPLD for zxbus  
/trunk/pdfs/74LVC1G08.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/pcad/zxinet.sch
33 2012-11-12 10:15:27 lvd /trunk/cpld/ trying to add gate-level  
/trunk/cpld/rtl/tb/cg
/trunk/cpld/rtl/tb/testbench
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/tb/c
/trunk/cpld/rtl/tb/files
/trunk/cpld/rtl/tb/ssz80.v
/trunk/cpld/rtl/tb/tb.v
26 2012-11-04 15:13:22 lvd /trunk/ finished USB-part, ZXBUS-part  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/pcad/zxinet.sch
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
/trunk/pdfs/bc847.pdf
/trunk/pdfs/irlml6402.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
/trunk/pcad/libs/zxinet.lib
/trunk/pcad/zxinet.sch
/trunk/specs/specs.txt
22 2012-10-31 11:10:21 lvd /trunk/ changed specs: added BRDY read, added USB power control bits  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/specs/specs.txt
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qpf
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v