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Rev Age Author Path Log message Diff
66 2014-10-26 19:05:30 lvd /branches/clkfix/ Spawning new branch "clkfix" to try to fix glitches by adding extra clock to FPGA  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
9 2012-10-10 20:05:06 lvd /trunk/ updated specs a bit, started cpld project