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Rev Age Author Path Log message Diff
66 2014-10-26 19:05:30 lvd /branches/clkfix/cpld/rtl/tb/tb.v Spawning new branch "clkfix" to try to fix glitches by adding extra clock to FPGA  
60 2013-10-03 10:12:41 lvd /branches/clkfix/cpld/rtl/tb/tb.v zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /branches/clkfix/cpld/rtl/tb/tb.v zxiznet: trying to fix glitches...  
35 2012-11-12 16:23:58 lvd /branches/clkfix/cpld/rtl/tb/tb.v gate-level passed  
33 2012-11-12 10:15:27 lvd /branches/clkfix/cpld/rtl/tb/tb.v trying to add gate-level  
32 2012-11-11 22:20:16 lvd /branches/clkfix/cpld/rtl/tb/tb.v added port access to w5300 (HDL code, testbench, specs all updated)  
31 2012-11-11 20:04:06 lvd /branches/clkfix/cpld/rtl/tb/tb.v finished testbench for current cpld code  
30 2012-11-11 16:03:39 lvd /branches/clkfix/cpld/rtl/tb/tb.v basic tests OK  
29 2012-11-11 10:20:58 lvd /branches/clkfix/cpld/rtl/tb/tb.v started writing testbench tests  
28 2012-11-07 06:09:01 lvd /branches/clkfix/cpld/rtl/tb/tb.v updated tb a little  
23 2012-10-31 11:25:00 lvd /branches/clkfix/cpld/rtl/tb/tb.v updated verilog code according to new specs  
16 2012-10-22 01:35:08 lvd /branches/clkfix/cpld/rtl/tb/tb.v updated testbench a little  
15 2012-10-17 13:53:57 lvd /branches/clkfix/cpld/rtl/tb/tb.v updated testbench