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Rev Age Author Path Log message Diff
25 2012-11-03 23:41:28 lvd /trunk/cpld/quartus/top.pof added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
22 2012-10-31 11:10:21 lvd /trunk/cpld/quartus/top.pof changed specs: added BRDY read, added USB power control bits  
13 2012-10-13 19:38:42 lvd /trunk/cpld/quartus/top.pof initial verilog code and quartus project (not tested\!)  

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