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Rev Age Author Path Log message Diff
37 2009-12-06 00:21:46 lvd /fpga/sdload/trunk/sim_top/tb_top.v Added timing info for z84c0010, tmpz84c00ap-8 and z0840008, modelling with z0840008 timings  
34 2009-12-05 12:25:39 lvd /fpga/sdload/trunk/sim_top/tb_top.v tb somehow works, added timing info (oscillospoce screenshots) to z80/clocking  
33 2009-12-04 00:39:35 lvd /fpga/sdload/trunk/sim_top/tb_top.v fixed bugs with Pullup1 going to vhld model  
31 2009-12-03 21:38:49 lvd /fpga/sdload/trunk/sim_top/tb_top.v T80 does not work in simulation  
29 2009-12-03 00:09:33 lvd /fpga/sdload/trunk/sim_top/tb_top.v complete testbench. does not work.  

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