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Rev Age Author Path Log message Diff Changes
31 2012-11-11 20:04:06 lvd /trunk/cpld/ finished testbench for current cpld code  
/trunk/cpld/quartus/top.pof
/trunk/cpld/rtl/tb/tb.v
26 2012-11-04 15:13:22 lvd /trunk/ finished USB-part, ZXBUS-part  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/pcad/zxinet.sch
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
/trunk/pdfs/bc847.pdf
/trunk/pdfs/irlml6402.pdf
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/zbus.v
/trunk/pcad/libs/zxinet.lib
/trunk/pcad/zxinet.sch
/trunk/specs/specs.txt
22 2012-10-31 11:10:21 lvd /trunk/ changed specs: added BRDY read, added USB power control bits  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qsf
/trunk/specs/specs.txt
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)  
/trunk/cpld/quartus/top.pof
/trunk/cpld/quartus/top.qpf
/trunk/cpld/quartus/top.qsf
/trunk/cpld/rtl/ports.v
/trunk/cpld/rtl/top.v
/trunk/cpld/rtl/wizmap.v
/trunk/cpld/rtl/zbus.v

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