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934 2021-03-21 18:11:04 lvd /fpga/base_trdemu/trunk/sim_top/tb_trdemu/ base_trdemu: updated test to check write disable during INI  
929 2021-02-28 19:57:50 lvd /fpga/base_trdemu/trunk/ fpga: trdemu: added write disable to prevent writes to page FE when INI is executed  
905 2020-11-15 16:52:48 lvd / fpga: trdemu: changing dir structure  
896 2020-11-14 20:24:33 lvd / pentevo: changing repo structure  
871 2020-02-26 13:02:15 lvd /fpga/trdemu/ fpga: trdemu: added port FF readback, trap-after-write. updated test  
870 2020-02-23 18:46:41 lvd /fpga/trdemu/sim_top/tb_trdemu/ fpga: trdemu: test update  
869 2020-02-23 18:38:20 lvd /fpga/trdemu/sim_top/tb_trdemu/ fpga: trdemu: test update  
867 2020-02-22 21:42:13 lvd /fpga/trdemu/ fpga: trdemu: removed VG93 chipselect when fdd_mask is 1, TODO: remove port FF trapping, add readback for port FF  
866 2020-02-22 20:31:12 lvd /fpga/trdemu/ fpga: trdemu: basic functions, TODO: subtle effects  
865 2020-02-20 21:38:40 lvd /fpga/trdemu/sim_top/tb_trdemu/ fpga: trdemu: updated test ROM  
864 2020-02-20 21:12:40 lvd /fpga/trdemu/ fpga: trying to run new tb  
863 2020-02-20 17:34:38 lvd /fpga/trdemu/ fpga: spawned new simulation dir