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Rev Age Author Path Log message Diff
122 2014-05-18 15:36:48 lvd /cpld/cpld6_revC_onlyclock/ ngs: added onlyclock version of CPLD for rev.C board  
66 2011-01-17 02:12:30 lvd /cpld/cpld5_buf/ cpld: fix by CHRV for no glitches  
60 2010-11-23 12:13:09 lvd / rebuilt both cpld5 and fpgaF with Q72, updated a little NGS_prm  
58 2010-09-25 12:15:49 lvd / cpld5_buf: recompiled with slow slew rate; added ramtests (fast and slow, slow for many freqs, fast for 24 only)  
49 2010-07-26 08:49:05 lvd /cpld/cpld5_buf/ updated pinout of CPLD for current .sch  
40 2010-05-15 13:07:59 chrv /cpld/cpld5_buf/ pin assigment (equal sch)  
37 2010-04-29 22:32:25 lvd /cpld/cpld5_buf/sim/ gate-level passes test!  
34 2010-04-21 23:23:36 lvd /cpld/cpld5_buf/ next iteration...  
33 2010-04-20 11:33:19 lvd /cpld/cpld5_buf/sim/ small correctons; gate level does not work yet  
32 2010-04-19 10:00:38 lvd /cpld/cpld5_buf/sim/ small update to filelist in cpld_buf/sim  
31 2010-04-19 01:24:11 lvd /cpld/cpld5_buf/sim/ small update to previous  
30 2010-04-19 01:05:31 lvd /cpld/cpld5_buf/ testbench for cpld_buf finished and works with rtl, todo: run testbench on gate-level  
29 2010-04-16 00:57:41 lvd /cpld/cpld5_buf/sim/ cpld tb up to fpga handover  
28 2010-04-15 01:04:37 lvd /cpld/cpld5_buf/ testbench update in progress...  
27 2010-04-14 10:28:14 lvd / rommap test done for rtl  
26 2010-04-12 10:35:28 lvd /cpld/cpld5_buf/sim/ same as below  
25 2010-04-09 23:26:34 lvd /cpld/cpld5_buf/ writing testbench for cpld_buf in progress  
24 2010-04-08 08:40:44 lvd /cpld/cpld5_buf/sim/ clock switcher testbench  
23 2010-04-07 23:58:41 lvd /cpld/cpld5_buf/sim/ Qua simulator suxx: using modelsim  
22 2010-04-04 12:38:56 lvd /cpld/cpld5_buf/ testing of cpld_buf begins  

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