| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 65 |
2013-11-10 00:38:45 |
lvd |
/branches/glitch_fixes/cpld/rtl/ |
zxiznet: glitch_fixes branch: returned LCELLS parameter to 1 |
|
| 63 |
2013-10-05 21:39:42 |
lvd |
/branches/glitch_fixes/cpld/ |
zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6 |
|
| 61 |
2013-10-03 10:13:46 |
lvd |
/branches/glitch_fixes/ |
branching glitch fixes code |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/trunk/cpld/ |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/trunk/cpld/ |
zxiznet: trying to fix glitches... |
|
| 58 |
2013-09-22 20:18:15 |
lvd |
/trunk/cpld/ |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
| 48 |
2013-04-04 00:17:48 |
lvd |
/trunk/ |
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built |
|
| 35 |
2012-11-12 16:23:58 |
lvd |
/trunk/cpld/rtl/tb/ |
gate-level passed |
|
| 34 |
2012-11-12 13:02:38 |
lvd |
/trunk/cpld/rtl/tb/ |
small update tp gate-level build script |
|
| 33 |
2012-11-12 10:15:27 |
lvd |
/trunk/cpld/ |
trying to add gate-level |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/trunk/ |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 31 |
2012-11-11 20:04:06 |
lvd |
/trunk/cpld/ |
finished testbench for current cpld code |
|
| 30 |
2012-11-11 16:03:39 |
lvd |
/trunk/cpld/rtl/ |
basic tests OK |
|
| 29 |
2012-11-11 10:20:58 |
lvd |
/trunk/cpld/rtl/tb/ |
started writing testbench tests |
|
| 28 |
2012-11-07 06:09:01 |
lvd |
/trunk/cpld/rtl/tb/ |
updated tb a little |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/trunk/ |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 23 |
2012-10-31 11:25:00 |
lvd |
/trunk/cpld/rtl/ |
updated verilog code according to new specs |
|
| 16 |
2012-10-22 01:35:08 |
lvd |
/trunk/cpld/rtl/tb/ |
updated testbench a little |
|
| 15 |
2012-10-17 13:53:57 |
lvd |
/trunk/cpld/rtl/tb/ |
updated testbench |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/trunk/cpld/ |
initial verilog code and quartus project (not tested\!) |
|