| Rev |
Age |
Author |
Path |
Log message |
Diff |
| 63 |
2013-10-05 21:39:42 |
lvd |
/branches/glitch_fixes/cpld/ |
zxiznet: changed to epm3128, added variable lcell delay, using delayed rd,wr,iorq everywhere, not functioning at all with LCELLS=7, still USB glitches with LCELLS=6 |
|
| 61 |
2013-10-03 10:13:46 |
lvd |
/branches/glitch_fixes/ |
branching glitch fixes code |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/trunk/cpld/ |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/trunk/cpld/ |
zxiznet: trying to fix glitches... |
|
| 58 |
2013-09-22 20:18:15 |
lvd |
/trunk/cpld/ |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
| 52 |
2013-04-04 16:07:25 |
lvd |
/trunk/cpld/quartus/ |
zxiznet: fixed nasty bug with not assigning pins and letting qva spread em randomly while changing RTL -- previous rev is therefore non-functional |
|
| 48 |
2013-04-04 00:17:48 |
lvd |
/trunk/ |
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built |
|
| 40 |
2012-11-17 11:13:07 |
lvd |
/trunk/ |
changed pins on CPLD for zxbus |
|
| 33 |
2012-11-12 10:15:27 |
lvd |
/trunk/cpld/ |
trying to add gate-level |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/trunk/ |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 31 |
2012-11-11 20:04:06 |
lvd |
/trunk/cpld/ |
finished testbench for current cpld code |
|
| 26 |
2012-11-04 15:13:22 |
lvd |
/trunk/ |
finished USB-part, ZXBUS-part |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/trunk/ |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 22 |
2012-10-31 11:10:21 |
lvd |
/trunk/ |
changed specs: added BRDY read, added USB power control bits |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/trunk/cpld/ |
initial verilog code and quartus project (not tested\!) |
|
| 9 |
2012-10-10 20:05:06 |
lvd |
/trunk/ |
updated specs a bit, started cpld project |
|