Subversion Repositories zxusbnet

Rev

Show changed files | Directory listing | RSS feed

Filtering Options

Rev Age Author Path Log message Diff
68 2014-10-26 21:51:58 lvd /branches/clkfix/cpld/quartus/ zxiznet: clkgen branch: successfull compilation of moved pinout  
67 2014-10-26 19:18:34 lvd /branches/clkfix/cpld/ clkfix: removing sl811_rst_n pin  
66 2014-10-26 19:05:30 lvd /branches/clkfix/ Spawning new branch "clkfix" to try to fix glitches by adding extra clock to FPGA  
62 2013-10-03 10:16:04 lvd /trunk/cpld/ zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
58 2013-09-22 20:18:15 lvd /trunk/cpld/ zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill  
52 2013-04-04 16:07:25 lvd /trunk/cpld/quartus/ zxiznet: fixed nasty bug with not assigning pins and letting qva spread em randomly while changing RTL -- previous rev is therefore non-functional  
48 2013-04-04 00:17:48 lvd /trunk/ zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built  
40 2012-11-17 11:13:07 lvd /trunk/ changed pins on CPLD for zxbus  
35 2012-11-12 16:23:58 lvd /trunk/cpld/rtl/tb/ gate-level passed  
34 2012-11-12 13:02:38 lvd /trunk/cpld/rtl/tb/ small update tp gate-level build script  
33 2012-11-12 10:15:27 lvd /trunk/cpld/ trying to add gate-level  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
31 2012-11-11 20:04:06 lvd /trunk/cpld/ finished testbench for current cpld code  
30 2012-11-11 16:03:39 lvd /trunk/cpld/rtl/ basic tests OK  
29 2012-11-11 10:20:58 lvd /trunk/cpld/rtl/tb/ started writing testbench tests  
28 2012-11-07 06:09:01 lvd /trunk/cpld/rtl/tb/ updated tb a little  
26 2012-11-04 15:13:22 lvd /trunk/ finished USB-part, ZXBUS-part  
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  

←Prev12Next→

Show All