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Rev Age Author Path Log message Diff
40 2009-12-08 00:12:49 lvd /fpga/base_trdemu/trunk/slave/ starting redesign from two clocks (zports.v) to single clock (fclk) and zpos-zneg strobes (zclock.v). May be broken now, not tested in hardware  
30 2009-12-03 00:09:55 lvd /fpga/base_trdemu/trunk/slave/ complete testbench. does not work.  
4 2009-11-21 21:06:56 lvd /fpga/base_trdemu/trunk/slave/ initial commit of FPGA files  

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