Rev |
Age |
Author |
Path |
Log message |
Diff |
83 |
2017-11-12 19:28:10 |
lvd |
/branches/newclk/cpld/rtl/ |
zxiznet: newclk: sim debugged |
|
82 |
2017-11-12 01:47:02 |
lvd |
/branches/newclk/cpld/rtl/ |
zxiznet: newclk: sim debugging |
|
81 |
2017-11-01 17:06:25 |
lvd |
/branches/newclk/cpld/rtl/ |
zxiznet: newclk: changing design |
|
80 |
2017-10-31 16:00:04 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: changing design |
|
79 |
2017-10-31 15:20:04 |
lvd |
/branches/newclk/ |
zxiznet: making branch for new clocking/filtering system |
|
78 |
2017-10-30 15:05:39 |
lvd |
/trunk/cpld/rtl/ |
zxiznet: comments added |
|
76 |
2017-09-28 15:00:24 |
lvd |
/trunk/ |
zxiznet: TODO updated |
|
75 |
2017-09-26 17:40:44 |
lvd |
/trunk/ |
zxiznet: revC TODO added |
|
72 |
2017-09-19 13:30:36 |
lvd |
/trunk/cpld/rtl/ |
trunk: added clocked filter, patched testbench to pass tests with that filter |
|
71 |
2017-09-19 11:08:25 |
lvd |
/trunk/cpld/rtl/tb/ |
trunk: fixed obvious bug in tests |
|
70 |
2017-09-18 00:15:06 |
dimkam |
/trunk/cpld/ |
patch |
|
62 |
2013-10-03 10:16:04 |
lvd |
/trunk/cpld/ |
zxiznet: trunk now is without bugfixes, all bugfixes is in branch/ dir |
|
60 |
2013-10-03 10:12:41 |
lvd |
/trunk/cpld/ |
zxiznet: dir structure |
|
59 |
2013-10-03 10:09:34 |
lvd |
/trunk/cpld/ |
zxiznet: trying to fix glitches... |
|
58 |
2013-09-22 20:18:15 |
lvd |
/trunk/cpld/ |
zxiznet: partially removed glitch problem by adding filters to cpld design, more glitches to kill |
|
48 |
2013-04-04 00:17:48 |
lvd |
/trunk/ |
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built |
|
35 |
2012-11-12 16:23:58 |
lvd |
/trunk/cpld/rtl/tb/ |
gate-level passed |
|
34 |
2012-11-12 13:02:38 |
lvd |
/trunk/cpld/rtl/tb/ |
small update tp gate-level build script |
|
33 |
2012-11-12 10:15:27 |
lvd |
/trunk/cpld/ |
trying to add gate-level |
|
32 |
2012-11-11 22:20:16 |
lvd |
/trunk/ |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
31 |
2012-11-11 20:04:06 |
lvd |
/trunk/cpld/ |
finished testbench for current cpld code |
|
30 |
2012-11-11 16:03:39 |
lvd |
/trunk/cpld/rtl/ |
basic tests OK |
|
29 |
2012-11-11 10:20:58 |
lvd |
/trunk/cpld/rtl/tb/ |
started writing testbench tests |
|
28 |
2012-11-07 06:09:01 |
lvd |
/trunk/cpld/rtl/tb/ |
updated tb a little |
|
25 |
2012-11-03 23:41:28 |
lvd |
/trunk/ |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
23 |
2012-10-31 11:25:00 |
lvd |
/trunk/cpld/rtl/ |
updated verilog code according to new specs |
|
16 |
2012-10-22 01:35:08 |
lvd |
/trunk/cpld/rtl/tb/ |
updated testbench a little |
|
15 |
2012-10-17 13:53:57 |
lvd |
/trunk/cpld/rtl/tb/ |
updated testbench |
|
13 |
2012-10-13 19:38:42 |
lvd |
/trunk/cpld/ |
initial verilog code and quartus project (not tested\!) |
|
9 |
2012-10-10 20:05:06 |
lvd |
/trunk/ |
updated specs a bit, started cpld project |
|