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Classic Timing Analyzer report for mainMon Nov 14 18:42:11 2011Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version---------------------; Table of Contents ;---------------------1. Legal Notice2. Timing Analyzer Summary3. Timing Analyzer Settings4. Clock Settings Summary5. Parallel Compilation6. Clock Setup: 'fclk'7. Clock Setup: 'spick'8. Clock Hold: 'fclk'9. Clock Hold: 'spick'10. tsu11. tco12. tpd13. th14. Ignored Timing Assignments15. Timing Analyzer Messages----------------; Legal Notice ;----------------Copyright (C) 1991-2009 Altera CorporationYour use of Altera Corporation's design tools, logic functionsand other software and tools, and its AMPP partner logicfunctions, and any output files from any of the foregoing(including device programming or simulation files), and anyassociated documentation or information are expressly subjectto the terms and conditions of the Altera Program LicenseSubscription Agreement, Altera MegaCore Function LicenseAgreement, or other applicable license agreement, including,without limitation, that your use is for the sole purpose ofprogramming logic devices manufactured by Altera and sold byAltera or its authorized distributors. Please refer to theapplicable agreement for further details.+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Summary ;+------------------------------+------------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+--------------+; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;+------------------------------+------------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+--------------+; Worst-case tsu ; N/A ; None ; 6.500 ns ; d[6] ; outdata[6] ; -- ; fclk ; 0 ;; Worst-case tco ; N/A ; None ; 20.200 ns ; bitptr[1] ; spidi ; spick ; -- ; 0 ;; Worst-case tpd ; N/A ; None ; 19.000 ns ; sddi ; spidi ; -- ; -- ; 0 ;; Worst-case th ; N/A ; None ; -0.600 ns ; spics_n ; number[0] ; -- ; spick ; 0 ;; Clock Setup: 'fclk' ; -1.286 ns ; 28.00 MHz ( period = 35.714 ns ) ; 27.03 MHz ( period = 37.000 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vred[1]~reg0 ; fclk ; fclk ; 16 ;; Clock Setup: 'spick' ; 176.344 ns ; 5.53 MHz ( period = 180.844 ns ) ; Restricted to 166.67 MHz ( period = 6.000 ns ) ; indata[4] ; indata[5] ; spick ; spick ; 0 ;; Clock Hold: 'fclk' ; 0.800 ns ; 28.00 MHz ( period = 35.714 ns ) ; N/A ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0 ;; Clock Hold: 'spick' ; 1.000 ns ; 5.53 MHz ( period = 180.844 ns ) ; N/A ; bitptr[0] ; bitptr[0] ; spick ; spick ; 0 ;; Total number of failed paths ; ; ; ; ; ; ; ; 16 ;+------------------------------+------------+----------------------------------+------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+--------------++-----------------------------------------------------------------------------------------------------------------------+; Timing Analyzer Settings ;+---------------------------------------------------------------------+--------------------+------+-------+-------------+; Option ; Setting ; From ; To ; Entity Name ;+---------------------------------------------------------------------+--------------------+------+-------+-------------+; Device Name ; EP1K50QC208-3 ; ; ; ;; Timing Models ; Final ; ; ; ;; Default hold multicycle ; Same as Multicycle ; ; ; ;; Cut paths between unrelated clock domains ; On ; ; ; ;; Cut off read during write signal paths ; On ; ; ; ;; Cut off feedback from I/O pins ; On ; ; ; ;; Report Combined Fast/Slow Timing ; Off ; ; ; ;; Ignore Clock Settings ; Off ; ; ; ;; Analyze latches as synchronous elements ; On ; ; ; ;; Enable Recovery/Removal analysis ; Off ; ; ; ;; Enable Clock Latency ; Off ; ; ; ;; Use TimeQuest Timing Analyzer ; Off ; ; ; ;; Number of source nodes to report per destination node ; 10 ; ; ; ;; Number of destination nodes to report ; 10 ; ; ; ;; Number of paths to report ; 200 ; ; ; ;; Report Minimum Timing Checks ; Off ; ; ; ;; Use Fast Timing Models ; Off ; ; ; ;; Report IO Paths Separately ; Off ; ; ; ;; Perform Multicorner Analysis ; Off ; ; ; ;; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;; Output I/O Timing Endpoint ; Near End ; ; ; ;; Clock Settings ; FPGA clock ; ; fclk ; ;; Clock Settings ; SPI clock ; ; spick ; ;+---------------------------------------------------------------------+--------------------+------+-------+-------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Settings Summary ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+; fclk ; FPGA clock ; User Pin ; 28.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;; spick ; SPI clock ; User Pin ; 5.53 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------++------------------------------------------+; Parallel Compilation ;+----------------------------+-------------+; Processors ; Number ;+----------------------------+-------------+; Number detected on machine ; 2 ;; Maximum allowed ; 2 ;; ; ;; Average used ; 1.00 ;; Maximum used ; 1 ;; ; ;; Usage by Processor ; % Time Used ;; 1 processor ; 100.0% ;; 2 processors ; 0.0% ;+----------------------------+-------------++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Setup: 'fclk' ;+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+; -1.286 ns ; 27.03 MHz ( period = 37.000 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.500 ns ;; -1.286 ns ; 27.03 MHz ( period = 37.000 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.500 ns ;; -1.186 ns ; 27.10 MHz ( period = 36.900 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.400 ns ;; -1.186 ns ; 27.10 MHz ( period = 36.900 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.400 ns ;; -1.186 ns ; 27.10 MHz ( period = 36.900 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.400 ns ;; -1.086 ns ; 27.17 MHz ( period = 36.800 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.300 ns ;; -1.086 ns ; 27.17 MHz ( period = 36.800 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.300 ns ;; -0.986 ns ; 27.25 MHz ( period = 36.700 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.200 ns ;; -0.986 ns ; 27.25 MHz ( period = 36.700 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.200 ns ;; -0.886 ns ; 27.32 MHz ( period = 36.600 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 34.100 ns ;; -0.486 ns ; 27.62 MHz ( period = 36.200 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.700 ns ;; -0.386 ns ; 27.70 MHz ( period = 36.100 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.600 ns ;; -0.286 ns ; 27.78 MHz ( period = 36.000 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.500 ns ;; -0.286 ns ; 27.78 MHz ( period = 36.000 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.500 ns ;; -0.186 ns ; 27.86 MHz ( period = 35.900 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.400 ns ;; -0.086 ns ; 27.93 MHz ( period = 35.800 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.300 ns ;; 0.014 ns ; 28.01 MHz ( period = 35.700 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 33.200 ns ;; 0.514 ns ; 28.41 MHz ( period = 35.200 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.700 ns ;; 0.514 ns ; 28.41 MHz ( period = 35.200 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.700 ns ;; 0.514 ns ; 28.41 MHz ( period = 35.200 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.700 ns ;; 0.614 ns ; 28.49 MHz ( period = 35.100 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.600 ns ;; 0.714 ns ; 28.57 MHz ( period = 35.000 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.500 ns ;; 0.814 ns ; 28.65 MHz ( period = 34.900 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.400 ns ;; 1.214 ns ; 28.99 MHz ( period = 34.500 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.000 ns ;; 1.214 ns ; 28.99 MHz ( period = 34.500 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 32.000 ns ;; 1.314 ns ; 29.07 MHz ( period = 34.400 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.900 ns ;; 1.314 ns ; 29.07 MHz ( period = 34.400 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.900 ns ;; 1.414 ns ; 29.15 MHz ( period = 34.300 ns ) ; scr_char[2] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.800 ns ;; 1.414 ns ; 29.15 MHz ( period = 34.300 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.800 ns ;; 1.514 ns ; 29.24 MHz ( period = 34.200 ns ) ; scr_char[2] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.700 ns ;; 1.514 ns ; 29.24 MHz ( period = 34.200 ns ) ; scr_char[3] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.700 ns ;; 1.514 ns ; 29.24 MHz ( period = 34.200 ns ) ; scr_char[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.700 ns ;; 1.514 ns ; 29.24 MHz ( period = 34.200 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.700 ns ;; 1.614 ns ; 29.33 MHz ( period = 34.100 ns ) ; scr_char[3] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.600 ns ;; 1.614 ns ; 29.33 MHz ( period = 34.100 ns ) ; scr_char[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.600 ns ;; 2.014 ns ; 29.67 MHz ( period = 33.700 ns ) ; scr_char[6] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.200 ns ;; 2.014 ns ; 29.67 MHz ( period = 33.700 ns ) ; scr_char[4] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.200 ns ;; 2.014 ns ; 29.67 MHz ( period = 33.700 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.200 ns ;; 2.014 ns ; 29.67 MHz ( period = 33.700 ns ) ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.200 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; scr_char[6] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; scr_char[4] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; scr_addr[5] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; scr_addr[4] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; scr_addr[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.114 ns ; 29.76 MHz ( period = 33.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.100 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[5] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[4] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[9] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[8] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[7] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[6] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[3] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[2] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.214 ns ; 29.85 MHz ( period = 33.500 ns ) ; scr_addr[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 31.000 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[9] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[8] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[7] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[6] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[3] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[2] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_addr[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_char[5] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.314 ns ; 29.94 MHz ( period = 33.400 ns ) ; scr_char[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.900 ns ;; 2.414 ns ; 30.03 MHz ( period = 33.300 ns ) ; scr_char[2] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.800 ns ;; 2.414 ns ; 30.03 MHz ( period = 33.300 ns ) ; scr_char[5] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.800 ns ;; 2.414 ns ; 30.03 MHz ( period = 33.300 ns ) ; scr_char[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.800 ns ;; 2.514 ns ; 30.12 MHz ( period = 33.200 ns ) ; scr_char[3] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.700 ns ;; 2.514 ns ; 30.12 MHz ( period = 33.200 ns ) ; scr_char[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.700 ns ;; 3.014 ns ; 30.58 MHz ( period = 32.700 ns ) ; scr_char[6] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.200 ns ;; 3.014 ns ; 30.58 MHz ( period = 32.700 ns ) ; scr_char[4] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.200 ns ;; 3.014 ns ; 30.58 MHz ( period = 32.700 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.200 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; scr_addr[5] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; scr_addr[4] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; scr_addr[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.114 ns ; 30.67 MHz ( period = 32.600 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.100 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_char[2] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[9] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[8] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[7] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[6] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[3] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[2] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.214 ns ; 30.77 MHz ( period = 32.500 ns ) ; scr_addr[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 30.000 ns ;; 3.314 ns ; 30.86 MHz ( period = 32.400 ns ) ; scr_char[3] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.900 ns ;; 3.314 ns ; 30.86 MHz ( period = 32.400 ns ) ; scr_char[1] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.900 ns ;; 3.314 ns ; 30.86 MHz ( period = 32.400 ns ) ; scr_char[5] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.900 ns ;; 3.314 ns ; 30.86 MHz ( period = 32.400 ns ) ; scr_char[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.900 ns ;; 3.814 ns ; 31.35 MHz ( period = 31.900 ns ) ; scr_char[6] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.400 ns ;; 3.814 ns ; 31.35 MHz ( period = 31.900 ns ) ; scr_char[4] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.400 ns ;; 3.814 ns ; 31.35 MHz ( period = 31.900 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.400 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; scr_addr[5] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; scr_addr[4] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; scr_addr[0] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 3.914 ns ; 31.45 MHz ( period = 31.800 ns ) ; scr_char[2] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.300 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[9] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[8] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[7] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[6] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[3] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[2] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_addr[1] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_char[3] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.014 ns ; 31.55 MHz ( period = 31.700 ns ) ; scr_char[1] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.200 ns ;; 4.114 ns ; 31.65 MHz ( period = 31.600 ns ) ; scr_char[5] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.100 ns ;; 4.114 ns ; 31.65 MHz ( period = 31.600 ns ) ; scr_char[0] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 29.100 ns ;; 4.514 ns ; 32.05 MHz ( period = 31.200 ns ) ; scr_char[6] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.700 ns ;; 4.514 ns ; 32.05 MHz ( period = 31.200 ns ) ; scr_char[4] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.700 ns ;; 4.514 ns ; 32.05 MHz ( period = 31.200 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.700 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; scr_addr[5] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; scr_addr[4] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; scr_addr[0] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.614 ns ; 32.15 MHz ( period = 31.100 ns ) ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.600 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[9] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[8] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[7] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[6] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[3] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[2] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.714 ns ; 32.26 MHz ( period = 31.000 ns ) ; scr_addr[1] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.500 ns ;; 4.814 ns ; 32.36 MHz ( period = 30.900 ns ) ; scr_char[5] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.400 ns ;; 4.814 ns ; 32.36 MHz ( period = 30.900 ns ) ; scr_char[0] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 28.400 ns ;; 10.614 ns ; 39.84 MHz ( period = 25.100 ns ) ; vcharline[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.600 ns ;; 10.614 ns ; 39.84 MHz ( period = 25.100 ns ) ; vcharline[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.600 ns ;; 10.714 ns ; 40.00 MHz ( period = 25.000 ns ) ; vcharline[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.500 ns ;; 10.714 ns ; 40.00 MHz ( period = 25.000 ns ) ; vcharline[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.500 ns ;; 11.114 ns ; 40.65 MHz ( period = 24.600 ns ) ; vcharline[2] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.100 ns ;; 11.214 ns ; 40.82 MHz ( period = 24.500 ns ) ; vcharline[2] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 22.000 ns ;; 11.614 ns ; 41.49 MHz ( period = 24.100 ns ) ; vcharline[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 21.600 ns ;; 11.614 ns ; 41.49 MHz ( period = 24.100 ns ) ; vcharline[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 21.600 ns ;; 12.114 ns ; 42.37 MHz ( period = 23.600 ns ) ; vcharline[2] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 21.100 ns ;; 12.414 ns ; 42.92 MHz ( period = 23.300 ns ) ; vcharline[1] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 20.800 ns ;; 12.414 ns ; 42.92 MHz ( period = 23.300 ns ) ; vcharline[0] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 20.800 ns ;; 12.914 ns ; 43.86 MHz ( period = 22.800 ns ) ; vcharline[2] ; vblu[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 20.300 ns ;; 13.114 ns ; 44.25 MHz ( period = 22.600 ns ) ; vcharline[1] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 20.100 ns ;; 13.114 ns ; 44.25 MHz ( period = 22.600 ns ) ; vcharline[0] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 20.100 ns ;; 13.614 ns ; 45.25 MHz ( period = 22.100 ns ) ; vcharline[2] ; vred[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 19.600 ns ;; 19.014 ns ; 59.88 MHz ( period = 16.700 ns ) ; hcount[1] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 14.200 ns ;; 19.114 ns ; 60.24 MHz ( period = 16.600 ns ) ; hcount[1] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 14.100 ns ;; 19.114 ns ; 60.24 MHz ( period = 16.600 ns ) ; hcount[0] ; vred[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 14.100 ns ;; 19.214 ns ; 60.61 MHz ( period = 16.500 ns ) ; hcount[0] ; vgrn[0]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 14.000 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 19.914 ns ; 63.29 MHz ( period = 15.800 ns ) ; hcount[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.400 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 13.200 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.014 ns ; 63.69 MHz ( period = 15.700 ns ) ; hcount[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 14.300 ns ;; 20.114 ns ; 64.10 MHz ( period = 15.600 ns ) ; hcount[0] ; vgrn[1]~reg0 ; fclk ; fclk ; 35.714 ns ; 33.214 ns ; 13.100 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[6] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[6] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[5] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[5] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[2] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[0] ; vcount[9] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.414 ns ; 65.36 MHz ( period = 15.300 ns ) ; hcount[2] ; vcount[9] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.900 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[1] ; vcount[6] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[4] ; vcount[6] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[1] ; vcount[5] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[4] ; vcount[5] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[1] ; vcount[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[4] ; vcount[3] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; 20.514 ns ; 65.79 MHz ( period = 15.200 ns ) ; hcount[1] ; vcount[1] ; fclk ; fclk ; 35.714 ns ; 34.314 ns ; 13.800 ns ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------+--------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Setup: 'spick' ;+------------+----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;+------------+----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+; 176.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[4] ; indata[5] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 3.100 ns ;; 176.444 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[1] ; bitptr[2] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 3.000 ns ;; 176.544 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[0] ; bitptr[2] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.900 ns ;; 177.144 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[0] ; indata[1] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.300 ns ;; 177.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[0] ; bitptr[1] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.200 ns ;; 177.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[1] ; number[2] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.200 ns ;; 177.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[2] ; number[3] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.200 ns ;; 177.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[0] ; number[1] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.200 ns ;; 177.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[2] ; indata[3] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.100 ns ;; 177.444 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[4] ; number[5] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.000 ns ;; 177.444 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[3] ; number[4] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 2.000 ns ;; 178.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[2] ; bitptr[2] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.200 ns ;; 178.244 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[1] ; bitptr[1] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.200 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; bitptr[0] ; bitptr[0] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[5] ; number[6] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[6] ; indata[7] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[5] ; indata[6] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[3] ; indata[4] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; indata[1] ; indata[2] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;; 178.344 ns ; Restricted to 166.67 MHz ( period = 6.0 ns ) ; number[6] ; number[7] ; spick ; spick ; 180.844 ns ; 179.444 ns ; 1.100 ns ;+------------+----------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Hold: 'fclk' ;+-----------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;+-----------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------+; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.800 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 0.900 ns ;; 0.900 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 0.900 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.000 ns ;; 1.000 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; spicsn_resync[0] ; spicsn_resync[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; main_osc[0] ; main_osc[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; main_osc[1] ; main_osc[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; main_osc[1] ; main_osc[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.100 ns ; scr_wren_c ; scr_wren_c ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; vcharline[2] ; vcharline[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; vcharline[1] ; vcharline[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; vcharline[0] ; vcharline[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; hcount[0] ; hcount[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; hsync ; hsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; hblank ; hblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; main_osc[0] ; main_osc[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; main_osc[0] ; main_osc[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; main_osc[2] ; main_osc[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.200 ns ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 1.300 ns ;; 2.000 ns ; vcount[9] ; vsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.100 ns ;; 2.100 ns ; hcount[8] ; hblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.100 ns ; vcount[9] ; vblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.200 ns ; hcount[5] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.300 ns ;; 2.200 ns ; hcount[5] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.300 ns ;; 2.200 ns ; hcount[5] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.300 ns ;; 2.600 ns ; vcount[8] ; vcount[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.700 ns ;; 2.600 ns ; vcount[7] ; vblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.700 ns ;; 2.700 ns ; vcount[3] ; vcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; vcount[1] ; vcount[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; vcount[4] ; vcount[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; hcount[1] ; hcount[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; main_osc[0] ; hcount[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; main_osc[1] ; hcount[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; hcount[2] ; hcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; hcount[3] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; vcount[2] ; vcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; hcount[8] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; csync ; csync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; vcount[9] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; vcount[7] ; vsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; main_osc[0] ; hsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.700 ns ; main_osc[1] ; hsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.800 ns ;; 2.800 ns ; scr_addr[7] ; scr_addr[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[6] ; scr_addr[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[5] ; scr_addr[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[4] ; scr_addr[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[3] ; scr_addr[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[2] ; scr_addr[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_addr[1] ; scr_addr[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; vcharline[0] ; vcharline[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_tv_mode ; vcharline[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; scr_tv_mode ; vcharline[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; vcount[6] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; vcount[5] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; hcount[6] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; hcount[7] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.800 ns ; vblank ; vblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.900 ns ; vcharline[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; vcharline[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; vcharline[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; vcharline[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; vcharline[2] ; lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; scr_addr[9] ; scr_addr[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; scr_addr[8] ; scr_addr[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 2.900 ns ; vsync ; vsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 3.100 ns ; vcount[2] ; vcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.200 ns ;; 3.100 ns ; hcount[0] ; hcount[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.200 ns ;; 3.100 ns ; hcount[1] ; hcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.200 ns ;; 3.100 ns ; hcount[2] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.200 ns ;; 3.100 ns ; vcount[1] ; vcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.200 ns ;; 3.200 ns ; vcount[5] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.200 ns ; vcount[1] ; vcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.200 ns ; hcount[0] ; hcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.200 ns ; hcount[1] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.200 ns ; hcount[6] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.200 ns ; hcount[7] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.300 ns ;; 3.300 ns ; scr_addr[5] ; scr_addr[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.400 ns ;; 3.300 ns ; vblank ; vcharline[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.400 ns ;; 3.300 ns ; vblank ; vcharline[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.400 ns ;; 3.300 ns ; hcount[0] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.400 ns ;; 3.300 ns ; hcount[6] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.400 ns ;; 3.400 ns ; scr_addr[4] ; scr_addr[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.500 ns ;; 3.400 ns ; vcount[6] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.500 ns ;; 3.500 ns ; scr_addr[0] ; scr_addr[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.500 ns ; vblank ; vcharline[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.500 ns ; vcount[3] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.500 ns ; spicsn_resync[1] ; flash_data_out[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.500 ns ; spicsn_resync[1] ; flash_data_out[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.500 ns ; vcount[5] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.600 ns ;; 3.600 ns ; scr_addr[4] ; scr_addr[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; vcount[3] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; vcount[2] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; hcount[3] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; spicsn_resync[0] ; flash_data_out[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; spicsn_resync[0] ; flash_data_out[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.600 ns ; hcount[7] ; hblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.700 ns ;; 3.700 ns ; vcount[8] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; vcount[2] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; vcount[1] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; vcount[8] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; hcount[2] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; hcount[3] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.700 ns ; vcount[8] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.800 ns ;; 3.800 ns ; scr_addr[0] ; scr_addr[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[0] ; vcharline[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[1] ; vcharline[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; vcount[1] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; vcount[4] ; vcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; vcount[4] ; vcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; hcount[1] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[0] ; hcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[1] ; hcount[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; hcount[2] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; hcount[3] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; spicsn_resync[1] ; flash_data_out[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[0] ; csync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[1] ; csync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; vcount[4] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[0] ; hblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; main_osc[1] ; hblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.800 ns ; vcount[2] ; vblank ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 3.900 ns ;; 3.900 ns ; main_osc[0] ; hcount[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; hcount[0] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[6] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; hcount[1] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; hcount[2] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[0] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; main_osc[1] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; spicsn_resync[0] ; flash_data_out[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; vcount[3] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 3.900 ns ; vcount[2] ; vsync ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.000 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; scr_addr[0] ; scr_addr[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[0] ; hcount[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; hcount[1] ; hcount[8] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; spicsn_resync[1] ; flash_data_out[7] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.000 ns ; vcount[2] ; vcount[9] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.100 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hblank ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hblank ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hblank ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hblank ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hblank ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[0] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; 4.100 ns ; hcount[2] ; lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0] ; fclk ; fclk ; 0.000 ns ; 0.100 ns ; 4.200 ns ;; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ;+-----------------------------------------+-----------------------------------------------------------------------------+-----------------------------------------------------------------------------+------------+----------+----------------------------+----------------------------+--------------------------++----------------------------------------------------------------------------------------------------------------------------------------------------+; Clock Hold: 'spick' ;+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------+; 1.000 ns ; bitptr[0] ; bitptr[0] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; number[5] ; number[6] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; indata[6] ; indata[7] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; indata[5] ; indata[6] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; indata[3] ; indata[4] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; indata[1] ; indata[2] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.000 ns ; number[6] ; number[7] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.100 ns ;; 1.100 ns ; bitptr[2] ; bitptr[2] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.100 ns ; bitptr[1] ; bitptr[1] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 1.200 ns ;; 1.900 ns ; number[4] ; number[5] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.000 ns ;; 1.900 ns ; number[3] ; number[4] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.000 ns ;; 2.000 ns ; indata[2] ; indata[3] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.100 ns ;; 2.100 ns ; bitptr[0] ; bitptr[1] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.100 ns ; number[1] ; number[2] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.100 ns ; number[2] ; number[3] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.100 ns ; number[0] ; number[1] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.200 ns ;; 2.200 ns ; indata[0] ; indata[1] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.300 ns ;; 2.800 ns ; bitptr[0] ; bitptr[2] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 2.900 ns ;; 2.900 ns ; bitptr[1] ; bitptr[2] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 3.000 ns ;; 3.000 ns ; indata[4] ; indata[5] ; spick ; spick ; 0.000 ns ; 0.100 ns ; 3.100 ns ;+---------------+-----------+-----------+------------+----------+----------------------------+----------------------------+--------------------------++---------------------------------------------------------------------------+; tsu ;+-------+--------------+------------+---------+------------------+----------+; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;+-------+--------------+------------+---------+------------------+----------+; N/A ; None ; 6.500 ns ; d[6] ; outdata[6] ; fclk ;; N/A ; None ; 6.400 ns ; d[7] ; outdata[7] ; fclk ;; N/A ; None ; 6.300 ns ; d[3] ; outdata[3] ; fclk ;; N/A ; None ; 6.300 ns ; d[4] ; outdata[4] ; fclk ;; N/A ; None ; 6.300 ns ; d[5] ; outdata[5] ; fclk ;; N/A ; None ; 6.200 ns ; d[0] ; outdata[0] ; fclk ;; N/A ; None ; 6.100 ns ; d[1] ; outdata[1] ; fclk ;; N/A ; None ; 6.100 ns ; d[2] ; outdata[2] ; fclk ;; N/A ; None ; 5.800 ns ; spics_n ; indata[0] ; spick ;; N/A ; None ; 5.800 ns ; spics_n ; indata[1] ; spick ;; N/A ; None ; 5.800 ns ; spics_n ; indata[2] ; spick ;; N/A ; None ; 5.800 ns ; spics_n ; indata[3] ; spick ;; N/A ; None ; 5.800 ns ; spics_n ; indata[4] ; spick ;; N/A ; None ; 5.000 ns ; spics_n ; indata[5] ; spick ;; N/A ; None ; 5.000 ns ; spics_n ; indata[6] ; spick ;; N/A ; None ; 5.000 ns ; spics_n ; indata[7] ; spick ;; N/A ; None ; 5.000 ns ; spido ; number[0] ; spick ;; N/A ; None ; 4.900 ns ; spido ; indata[0] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[7] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[1] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; spicsn_resync[0] ; fclk ;; N/A ; None ; 2.100 ns ; spics_n ; number[6] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[4] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[5] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[3] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[2] ; spick ;; N/A ; None ; 2.100 ns ; spics_n ; number[0] ; spick ;+-------+--------------+------------+---------+------------------+----------++-------------------------------------------------------------------------------+; tco ;+-------+--------------+------------+-------------------+----------+------------+; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;+-------+--------------+------------+-------------------+----------+------------+; N/A ; None ; 20.200 ns ; bitptr[1] ; spidi ; spick ;; N/A ; None ; 20.100 ns ; number[6] ; spidi ; spick ;; N/A ; None ; 20.100 ns ; number[5] ; spidi ; spick ;; N/A ; None ; 20.100 ns ; bitptr[0] ; spidi ; spick ;; N/A ; None ; 20.000 ns ; number[7] ; spidi ; spick ;; N/A ; None ; 19.700 ns ; number[1] ; spidi ; spick ;; N/A ; None ; 19.700 ns ; number[6] ; sdclk ; spick ;; N/A ; None ; 19.700 ns ; number[5] ; sdclk ; spick ;; N/A ; None ; 19.600 ns ; number[2] ; spidi ; spick ;; N/A ; None ; 19.600 ns ; number[7] ; sdclk ; spick ;; N/A ; None ; 19.300 ns ; number[1] ; sdclk ; spick ;; N/A ; None ; 19.200 ns ; number[2] ; sdclk ; spick ;; N/A ; None ; 19.000 ns ; outdata[5] ; spidi ; fclk ;; N/A ; None ; 18.900 ns ; outdata[4] ; spidi ; fclk ;; N/A ; None ; 18.600 ns ; number[6] ; sdcs_n ; spick ;; N/A ; None ; 18.600 ns ; number[5] ; sdcs_n ; spick ;; N/A ; None ; 18.500 ns ; number[6] ; sddo ; spick ;; N/A ; None ; 18.500 ns ; number[5] ; sddo ; spick ;; N/A ; None ; 18.500 ns ; number[7] ; sdcs_n ; spick ;; N/A ; None ; 18.400 ns ; number[7] ; sddo ; spick ;; N/A ; None ; 18.200 ns ; number[1] ; sdcs_n ; spick ;; N/A ; None ; 18.100 ns ; number[1] ; sddo ; spick ;; N/A ; None ; 18.100 ns ; number[2] ; sdcs_n ; spick ;; N/A ; None ; 18.000 ns ; number[2] ; sddo ; spick ;; N/A ; None ; 17.400 ns ; outdata[6] ; spidi ; fclk ;; N/A ; None ; 17.200 ns ; outdata[7] ; spidi ; fclk ;; N/A ; None ; 17.200 ns ; outdata[1] ; spidi ; fclk ;; N/A ; None ; 17.100 ns ; outdata[0] ; spidi ; fclk ;; N/A ; None ; 16.700 ns ; flash_oe ; d[0] ; fclk ;; N/A ; None ; 16.600 ns ; flash_oe ; d[3] ; fclk ;; N/A ; None ; 16.600 ns ; flash_oe ; d[1] ; fclk ;; N/A ; None ; 16.600 ns ; flash_oe ; d[2] ; fclk ;; N/A ; None ; 16.600 ns ; flash_oe ; d[4] ; fclk ;; N/A ; None ; 16.600 ns ; flash_oe ; d[5] ; fclk ;; N/A ; None ; 16.600 ns ; number[0] ; spidi ; spick ;; N/A ; None ; 16.500 ns ; flash_oe ; d[7] ; fclk ;; N/A ; None ; 16.500 ns ; flash_oe ; d[6] ; fclk ;; N/A ; None ; 16.200 ns ; number[0] ; sdclk ; spick ;; N/A ; None ; 15.600 ns ; number[4] ; spidi ; spick ;; N/A ; None ; 15.600 ns ; outdata[2] ; spidi ; fclk ;; N/A ; None ; 15.400 ns ; outdata[3] ; spidi ; fclk ;; N/A ; None ; 15.200 ns ; number[4] ; sdclk ; spick ;; N/A ; None ; 15.100 ns ; number[0] ; sdcs_n ; spick ;; N/A ; None ; 15.000 ns ; number[0] ; sddo ; spick ;; N/A ; None ; 14.100 ns ; number[4] ; sdcs_n ; spick ;; N/A ; None ; 14.000 ns ; number[4] ; sddo ; spick ;; N/A ; None ; 14.000 ns ; flash_oe ; romoe_n ; fclk ;; N/A ; None ; 13.800 ns ; bitptr[2] ; spidi ; spick ;; N/A ; None ; 13.200 ns ; number[3] ; sdcs_n ; spick ;; N/A ; None ; 11.800 ns ; flash_data_out[4] ; d[4] ; fclk ;; N/A ; None ; 11.700 ns ; flash_data_out[1] ; d[1] ; fclk ;; N/A ; None ; 11.700 ns ; flash_addr[13] ; a[13] ; fclk ;; N/A ; None ; 11.600 ns ; flash_addr[11] ; a[11] ; fclk ;; N/A ; None ; 11.600 ns ; flash_addr[10] ; a[10] ; fclk ;; N/A ; None ; 11.600 ns ; flash_addr[9] ; a[9] ; fclk ;; N/A ; None ; 11.500 ns ; flash_data_out[0] ; d[0] ; fclk ;; N/A ; None ; 11.500 ns ; flash_data_out[7] ; d[7] ; fclk ;; N/A ; None ; 11.500 ns ; flash_addr[8] ; a[8] ; fclk ;; N/A ; None ; 11.400 ns ; flash_addr[0] ; a[0] ; fclk ;; N/A ; None ; 11.300 ns ; vsync ; vvsync ; fclk ;; N/A ; None ; 11.300 ns ; main_osc[2] ; clkz_out ; fclk ;; N/A ; None ; 11.200 ns ; flash_data_out[5] ; d[5] ; fclk ;; N/A ; None ; 11.200 ns ; flash_data_out[6] ; d[6] ; fclk ;; N/A ; None ; 11.100 ns ; flash_cs ; csrom ; fclk ;; N/A ; None ; 11.000 ns ; flash_data_out[3] ; d[3] ; fclk ;; N/A ; None ; 11.000 ns ; flash_data_out[2] ; d[2] ; fclk ;; N/A ; None ; 10.900 ns ; hsync ; vhsync ; fclk ;; N/A ; None ; 10.900 ns ; flash_addr[7] ; a[7] ; fclk ;; N/A ; None ; 10.900 ns ; flash_addr[6] ; a[6] ; fclk ;; N/A ; None ; 10.900 ns ; flash_addr[5] ; a[5] ; fclk ;; N/A ; None ; 10.800 ns ; flash_addr[12] ; a[12] ; fclk ;; N/A ; None ; 10.700 ns ; flash_addr[2] ; a[2] ; fclk ;; N/A ; None ; 10.700 ns ; flash_addr[1] ; a[1] ; fclk ;; N/A ; None ; 10.600 ns ; csync ; vcsync ; fclk ;; N/A ; None ; 10.500 ns ; flash_addr[3] ; a[3] ; fclk ;; N/A ; None ; 10.400 ns ; flash_addr[18] ; rompg4 ; fclk ;; N/A ; None ; 10.400 ns ; flash_addr[17] ; rompg3 ; fclk ;; N/A ; None ; 10.400 ns ; flash_addr[16] ; rompg2 ; fclk ;; N/A ; None ; 10.400 ns ; flash_addr[15] ; dos_n ; fclk ;; N/A ; None ; 10.400 ns ; flash_addr[14] ; rompg0_n ; fclk ;; N/A ; None ; 10.400 ns ; flash_we ; romwe_n ; fclk ;; N/A ; None ; 10.200 ns ; flash_addr[4] ; a[4] ; fclk ;; N/A ; None ; 7.300 ns ; vblu[1]~reg0 ; vblu[1] ; fclk ;; N/A ; None ; 7.300 ns ; vblu[0]~reg0 ; vblu[0] ; fclk ;; N/A ; None ; 7.300 ns ; vgrn[1]~reg0 ; vgrn[1] ; fclk ;; N/A ; None ; 7.300 ns ; vgrn[0]~reg0 ; vgrn[0] ; fclk ;; N/A ; None ; 7.300 ns ; vred[1]~reg0 ; vred[1] ; fclk ;; N/A ; None ; 7.300 ns ; vred[0]~reg0 ; vred[0] ; fclk ;+-------+--------------+------------+-------------------+----------+------------++-----------------------------------------------------------------+; tpd ;+-------+-------------------+-----------------+----------+--------+; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;+-------+-------------------+-----------------+----------+--------+; N/A ; None ; 19.000 ns ; sddi ; spidi ;; N/A ; None ; 15.100 ns ; spics_n ; spidi ;; N/A ; None ; 14.700 ns ; spics_n ; sdclk ;; N/A ; None ; 14.600 ns ; spido ; sddo ;; N/A ; None ; 13.600 ns ; spics_n ; sdcs_n ;; N/A ; None ; 13.500 ns ; spics_n ; sddo ;; N/A ; None ; 13.500 ns ; spiint_n ; beep ;; N/A ; None ; 11.100 ns ; spick ; sdclk ;+-------+-------------------+-----------------+----------+--------++---------------------------------------------------------------------------------+; th ;+---------------+-------------+-----------+---------+------------------+----------+; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;+---------------+-------------+-----------+---------+------------------+----------+; N/A ; None ; -0.600 ns ; spics_n ; number[7] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[1] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; spicsn_resync[0] ; fclk ;; N/A ; None ; -0.600 ns ; spics_n ; number[6] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[4] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[5] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[3] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[2] ; spick ;; N/A ; None ; -0.600 ns ; spics_n ; number[0] ; spick ;; N/A ; None ; -3.400 ns ; spido ; indata[0] ; spick ;; N/A ; None ; -3.500 ns ; spics_n ; indata[5] ; spick ;; N/A ; None ; -3.500 ns ; spics_n ; indata[6] ; spick ;; N/A ; None ; -3.500 ns ; spics_n ; indata[7] ; spick ;; N/A ; None ; -3.500 ns ; spido ; number[0] ; spick ;; N/A ; None ; -4.300 ns ; spics_n ; indata[0] ; spick ;; N/A ; None ; -4.300 ns ; spics_n ; indata[1] ; spick ;; N/A ; None ; -4.300 ns ; spics_n ; indata[2] ; spick ;; N/A ; None ; -4.300 ns ; spics_n ; indata[3] ; spick ;; N/A ; None ; -4.300 ns ; spics_n ; indata[4] ; spick ;; N/A ; None ; -4.600 ns ; d[1] ; outdata[1] ; fclk ;; N/A ; None ; -4.600 ns ; d[2] ; outdata[2] ; fclk ;; N/A ; None ; -4.700 ns ; d[0] ; outdata[0] ; fclk ;; N/A ; None ; -4.800 ns ; d[3] ; outdata[3] ; fclk ;; N/A ; None ; -4.800 ns ; d[4] ; outdata[4] ; fclk ;; N/A ; None ; -4.800 ns ; d[5] ; outdata[5] ; fclk ;; N/A ; None ; -4.900 ns ; d[7] ; outdata[7] ; fclk ;; N/A ; None ; -5.000 ns ; d[6] ; outdata[6] ; fclk ;+---------------+-------------+-----------+---------+------------------+----------++-------------------------------------------------------------------------------------------------------------------+; Ignored Timing Assignments ;+-----------------+-----------+--------+---------+-------------+----------------------------------------------------+; Option ; Setting ; From ; To ; Entity Name ; Help ;+-----------------+-----------+--------+---------+-------------+----------------------------------------------------+; Cut Timing Path ; On ; rddata ; zd_out ; ; No element named rddata was found in the netlist ;; Clock Settings ; Z80 clock ; ; clkz_in ; ; No timing path applicable to specified destination ;+-----------------+-----------+--------+---------+-------------+----------------------------------------------------++--------------------------+; Timing Analyzer Messages ;+--------------------------+Info: *******************************************************************Info: Running Quartus II Classic Timing AnalyzerInfo: Version 9.0 Build 132 02/25/2009 SJ Full VersionInfo: Processing started: Mon Nov 14 18:42:11 2011Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off fpga -c mainInfo: Parallel compilation is enabled and will use 2 of the 2 processors detectedInfo: Started post-fitting delay annotationInfo: Delay annotation completed successfullyWarning: Timing Analysis is analyzing one or more combinational loops as latchesWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[0]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[1]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[1]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[2]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[2]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[3]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[4]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[4]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[5]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[5]~mem_cell_din1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_wa1" is a latchWarning: Node "lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_din1" is a latchWarning: Clock Setting "Z80 clock" is unassignedInfo: Slack time is -1.286 ns for clock "fclk" between source register "lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]" and destination register "vred[1]~reg0"Info: Fmax is 27.03 MHz (period= 37.0 ns)Info: + Largest register to register requirement is 33.214 nsInfo: + Setup relationship between source and destination is 35.714 nsInfo: + Latch edge is 35.714 nsInfo: Clock period of Destination clock "fclk" is 35.714 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: - Launch edge is 0.000 nsInfo: Clock period of Source clock "fclk" is 35.714 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: + Largest clock skew is -0.500 nsInfo: + Shortest clock path from clock "fclk" to destination register is 3.000 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'Info: 2: + IC(0.400 ns) + CELL(0.400 ns) = 3.000 ns; Loc. = IOC_132; Fanout = 1; REG Node = 'vred[1]~reg0'Info: Total cell delay = 2.600 ns ( 86.67 % )Info: Total interconnect delay = 0.400 ns ( 13.33 % )Info: - Longest clock path from clock "fclk" to source register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_I16; Fanout = 3; REG Node = 'lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Micro clock to output delay of source is 0.700 nsInfo: - Micro setup delay of destination is 1.300 nsInfo: - Longest register to register delay is 34.500 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC6_I16; Fanout = 3; REG Node = 'lpm_counter:hcharcount_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]'Info: 2: + IC(1.300 ns) + CELL(0.600 ns) = 1.900 ns; Loc. = LC3_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~COUT'Info: 3: + IC(0.000 ns) + CELL(0.100 ns) = 2.000 ns; Loc. = LC4_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[3]~COUT'Info: 4: + IC(0.000 ns) + CELL(0.100 ns) = 2.100 ns; Loc. = LC5_I18; Fanout = 2; COMB Node = 'lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[4]~COUT'Info: 5: + IC(0.000 ns) + CELL(0.100 ns) = 2.200 ns; Loc. = LC6_I18; Fanout = 1; COMB Node = 'lpm_add_sub:Add6|addcore:adder|a_csnbuffer:result_node|cs_buffer[5]~COUT'Info: 6: + IC(0.000 ns) + CELL(1.300 ns) = 3.500 ns; Loc. = LC7_I18; Fanout = 7; COMB Node = 'lpm_add_sub:Add6|addcore:adder|unreg_res_node[6]'Info: 7: + IC(2.200 ns) + CELL(6.300 ns) = 12.000 ns; Loc. = EC10_H; Fanout = 1; MEM Node = 'lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]~mem_cell_ra0'Info: 8: + IC(0.000 ns) + CELL(0.000 ns) = 12.000 ns; Loc. = EC10_H; Fanout = 8; MEM Node = 'lpm_ram_dp0:scr_mem|lpm_ram_dp:lpm_ram_dp_component|altdpram:sram|q[6]'Info: 9: + IC(2.900 ns) + CELL(6.300 ns) = 21.200 ns; Loc. = EC9_G; Fanout = 1; MEM Node = 'lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]~mem_cell_ra0'Info: 10: + IC(0.000 ns) + CELL(0.000 ns) = 21.200 ns; Loc. = EC9_G; Fanout = 1; MEM Node = 'lpm_rom0:chargen|lpm_rom:lpm_rom_component|altrom:srom|q[0]'Info: 11: + IC(1.300 ns) + CELL(1.400 ns) = 23.900 ns; Loc. = LC2_G2; Fanout = 1; COMB Node = 'Mux0~4'Info: 12: + IC(0.200 ns) + CELL(1.500 ns) = 25.600 ns; Loc. = LC3_G2; Fanout = 1; COMB Node = 'Mux0~5'Info: 13: + IC(0.200 ns) + CELL(0.900 ns) = 26.700 ns; Loc. = LC7_G2; Fanout = 1; COMB Node = 'Mux0~15'Info: 14: + IC(0.000 ns) + CELL(1.500 ns) = 28.200 ns; Loc. = LC8_G2; Fanout = 5; COMB Node = 'Mux0~10'Info: 15: + IC(1.100 ns) + CELL(1.400 ns) = 30.700 ns; Loc. = LC6_G1; Fanout = 1; COMB Node = 'vred[1]~6'Info: 16: + IC(1.800 ns) + CELL(2.000 ns) = 34.500 ns; Loc. = IOC_132; Fanout = 1; REG Node = 'vred[1]~reg0'Info: Total cell delay = 23.500 ns ( 68.12 % )Info: Total interconnect delay = 11.000 ns ( 31.88 % )Warning: Can't achieve timing requirement Clock Setup: 'fclk' along 16 path(s). See Report window for details.Info: Slack time is 176.344 ns for clock "spick" between source register "indata[4]" and destination register "indata[5]"Info: Fmax is restricted to 166.67 MHz due to tcl and tch limitsInfo: + Largest register to register requirement is 179.444 nsInfo: + Setup relationship between source and destination is 180.844 nsInfo: + Latch edge is 180.844 nsInfo: Clock period of Destination clock "spick" is 180.844 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: - Launch edge is 0.000 nsInfo: Clock period of Source clock "spick" is 180.844 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: + Largest clock skew is 0.000 nsInfo: + Shortest clock path from clock "spick" to destination register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC6_H22; Fanout = 6; REG Node = 'indata[5]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Longest clock path from clock "spick" to source register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H4; Fanout = 6; REG Node = 'indata[4]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Micro clock to output delay of source is 0.700 nsInfo: - Micro setup delay of destination is 0.700 nsInfo: - Longest register to register delay is 3.100 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H4; Fanout = 6; REG Node = 'indata[4]'Info: 2: + IC(2.200 ns) + CELL(0.900 ns) = 3.100 ns; Loc. = LC6_H22; Fanout = 6; REG Node = 'indata[5]'Info: Total cell delay = 0.900 ns ( 29.03 % )Info: Total interconnect delay = 2.200 ns ( 70.97 % )Info: Minimum slack time is 800 ps for clock "fclk" between source register "lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]" and destination register "lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]"Info: + Shortest register to register delay is 0.900 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]'Info: 2: + IC(0.000 ns) + CELL(0.900 ns) = 0.900 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]'Info: Total cell delay = 0.900 ns ( 100.00 % )Info: - Smallest register to register requirement is 0.100 nsInfo: + Hold relationship between source and destination is 0.000 nsInfo: + Latch edge is 0.000 nsInfo: Clock period of Destination clock "fclk" is 35.714 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: Multicycle Hold factor for Destination register is 1Info: - Launch edge is 0.000 nsInfo: Clock period of Source clock "fclk" is 35.714 ns with offset of 0.000 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: Multicycle Hold factor for Source register is 1Info: + Smallest clock skew is 0.000 nsInfo: + Longest clock path from clock "fclk" to destination register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Shortest clock path from clock "fclk" to source register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_I17; Fanout = 2; REG Node = 'lpm_counter:voffset_rtl_1|alt_counter_f10ke:wysi_counter|counter_cell[4]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Micro clock to output delay of source is 0.700 nsInfo: + Micro hold delay of destination is 0.800 nsInfo: Minimum slack time is 1.0 ns for clock "spick" between source register "bitptr[0]" and destination register "bitptr[0]"Info: + Shortest register to register delay is 1.100 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr[0]'Info: 2: + IC(0.200 ns) + CELL(0.900 ns) = 1.100 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr[0]'Info: Total cell delay = 0.900 ns ( 81.82 % )Info: Total interconnect delay = 0.200 ns ( 18.18 % )Info: - Smallest register to register requirement is 0.100 nsInfo: + Hold relationship between source and destination is 0.000 nsInfo: + Latch edge is 90.422 nsInfo: Clock period of Destination clock "spick" is 180.844 ns with inverted offset of 90.422 ns and duty cycle of 50Info: Multicycle Setup factor for Destination register is 1Info: Multicycle Hold factor for Destination register is 1Info: - Launch edge is 90.422 nsInfo: Clock period of Source clock "spick" is 180.844 ns with inverted offset of 90.422 ns and duty cycle of 50Info: Multicycle Setup factor for Source register is 1Info: Multicycle Hold factor for Source register is 1Info: + Smallest clock skew is 0.000 nsInfo: + Longest clock path from clock "spick" to destination register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr[0]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Shortest clock path from clock "spick" to source register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC1_H21; Fanout = 5; REG Node = 'bitptr[0]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: - Micro clock to output delay of source is 0.700 nsInfo: + Micro hold delay of destination is 0.800 nsInfo: tsu for register "outdata[6]" (data pin = "d[6]", clock pin = "fclk") is 6.500 nsInfo: + Longest pin to register delay is 9.300 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_12; Fanout = 1; PIN Node = 'd[6]'Info: 2: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = IOC_12; Fanout = 1; COMB Node = 'd[6]~9'Info: 3: + IC(5.300 ns) + CELL(1.000 ns) = 9.300 ns; Loc. = LC3_H20; Fanout = 1; REG Node = 'outdata[6]'Info: Total cell delay = 4.000 ns ( 43.01 % )Info: Total interconnect delay = 5.300 ns ( 56.99 % )Info: + Micro setup delay of destination is 0.700 nsInfo: - Shortest clock path from clock "fclk" to destination register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_183; Fanout = 106; CLK Node = 'fclk'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC3_H20; Fanout = 1; REG Node = 'outdata[6]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: tco from clock "spick" to destination pin "spidi" through register "bitptr[1]" is 20.200 nsInfo: + Longest clock path from clock "spick" to source register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC2_H24; Fanout = 6; REG Node = 'bitptr[1]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: + Micro clock to output delay of source is 0.700 nsInfo: + Longest register to pin delay is 16.000 nsInfo: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_H24; Fanout = 6; REG Node = 'bitptr[1]'Info: 2: + IC(1.300 ns) + CELL(1.600 ns) = 2.900 ns; Loc. = LC6_H20; Fanout = 1; COMB Node = 'Mux1~0'Info: 3: + IC(0.200 ns) + CELL(1.500 ns) = 4.600 ns; Loc. = LC2_H20; Fanout = 1; COMB Node = 'Mux1~1'Info: 4: + IC(1.900 ns) + CELL(1.500 ns) = 8.000 ns; Loc. = LC7_H2; Fanout = 1; COMB Node = 'spidi~1'Info: 5: + IC(0.200 ns) + CELL(1.600 ns) = 9.800 ns; Loc. = LC5_H2; Fanout = 1; COMB Node = 'spidi~2'Info: 6: + IC(1.300 ns) + CELL(4.900 ns) = 16.000 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'spidi'Info: Total cell delay = 11.100 ns ( 69.38 % )Info: Total interconnect delay = 4.900 ns ( 30.63 % )Info: Longest tpd from source pin "sddi" to destination pin "spidi" is 19.000 nsInfo: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_115; Fanout = 1; PIN Node = 'sddi'Info: 2: + IC(6.400 ns) + CELL(1.600 ns) = 11.000 ns; Loc. = LC7_H2; Fanout = 1; COMB Node = 'spidi~1'Info: 3: + IC(0.200 ns) + CELL(1.600 ns) = 12.800 ns; Loc. = LC5_H2; Fanout = 1; COMB Node = 'spidi~2'Info: 4: + IC(1.300 ns) + CELL(4.900 ns) = 19.000 ns; Loc. = PIN_158; Fanout = 0; PIN Node = 'spidi'Info: Total cell delay = 11.100 ns ( 58.42 % )Info: Total interconnect delay = 7.900 ns ( 41.58 % )Info: th for register "number[7]" (data pin = "spics_n", clock pin = "spick") is -0.600 nsInfo: + Longest clock path from clock "spick" to destination register is 3.500 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_184; Fanout = 20; CLK Node = 'spick'Info: 2: + IC(1.300 ns) + CELL(0.000 ns) = 3.500 ns; Loc. = LC7_H3; Fanout = 5; REG Node = 'number[7]'Info: Total cell delay = 2.200 ns ( 62.86 % )Info: Total interconnect delay = 1.300 ns ( 37.14 % )Info: + Micro hold delay of destination is 0.800 nsInfo: - Shortest pin to register delay is 4.900 nsInfo: 1: + IC(0.000 ns) + CELL(2.200 ns) = 2.200 ns; Loc. = PIN_182; Fanout = 14; PIN Node = 'spics_n'Info: 2: + IC(1.800 ns) + CELL(0.900 ns) = 4.900 ns; Loc. = LC7_H3; Fanout = 5; REG Node = 'number[7]'Info: Total cell delay = 3.100 ns ( 63.27 % )Info: Total interconnect delay = 1.800 ns ( 36.73 % )Critical Warning: Timing requirements for slow timing model timing analysis were not met. See Report window for details.Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for detailsInfo: Quartus II Classic Timing Analyzer was successful. 0 errors, 19 warningsInfo: Peak virtual memory: 135 megabytesInfo: Processing ended: Mon Nov 14 18:42:12 2011Info: Elapsed time: 00:00:01Info: Total CPU time (on all processors): 00:00:01