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;LAST UPDATE: 10.09.2014 savelij
IREG_E EQU ADR_RST8END-0X50 ;1
IREG_D EQU IREG_E+1 ;1
IREG_L EQU IREG_D+1 ;1
IREG_H EQU IREG_L+1 ;1
DOS_STEK EQU IREG_H+1 ;2
BYTE_DRIVE EQU DOS_STEK+2 ;1
/
/
WR_1F EQU BYTE_DRIVE+1 ;1 1F (
)
RD_1F EQU WR_1F+1 ;1
1F
PORT_3F EQU RD_1F+1 ;1
3F
PORT_5F EQU PORT_3F+1 ;1
5F
PORT_7F EQU PORT_5F+1 ;1
7F
WR_FF EQU PORT_7F+1 ;1 FF
RD_FF EQU WR_FF+1 ;1
FF
BUFF_SECT EQU RD_FF+1 ;2
/
ADDR_RET EQU BUFF_SECT+2 ;2
REG_IF EQU ADDR_RET+2 ;1
REG_I EQU REG_IF+1 ;1
REG_C EQU REG_I+1 ;1
REG_B EQU REG_C+1 ;1
REG_F EQU REG_B+1 ;1
REG_A EQU REG_F+1 ;1
REG_L EQU REG_A+1 ;1
/
REG_H EQU REG_L+1 ;1
WR_BF EQU REG_H+1 ;1
WR_77 EQU WR_BF+1 ;1
WR_EFF7 EQU WR_77+1 ;1
WR_7FFD EQU WR_EFF7+1 ;1
WR_DOS7FFD EQU WR_7FFD+1 ;1
WR_RAMNROM EQU WR_DOS7FFD+1 ;1
WR_1WINA3 EQU WR_RAMNROM+1 ;1
WR_1WINA2 EQU WR_1WINA3+1 ;1
WR_1WINA1 EQU WR_1WINA2+1 ;1
WR_1WINA0 EQU WR_1WINA1+1 ;1
WR_0WINA3 EQU WR_1WINA0+1 ;1
WR_0WINA2 EQU WR_0WINA3+1 ;1
WR_0WINA1 EQU WR_0WINA2+1 ;1
WR_0WINA0 EQU WR_0WINA1+1 ;1
BB_CPU1 EQU WR_0WINA0+1 ;1 CPU1
BP_CPU1 EQU BB_CPU1+1 ;1
CPU1
BB_CPU2 EQU BP_CPU1+1 ;1 CPU2
BP_CPU2 EQU BB_CPU2+1 ;1
CPU2
MINT_STACK EQU BP_CPU2+1 ;2
TEK_ROMPAGE EQU MINT_STACK+2 ;1
MASK_MNT_DRV EQU TEK_ROMPAGE+1 ;1
MASK_WRK_DRV EQU MASK_MNT_DRV+1 ;1
TEMP_SP EQU MASK_WRK_DRV+1 ;2
SAVED_RAM EQU TEMP_SP+2 ;10
END_VARS