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  1. `include "../include/tune.v"
  2.  
  3. // PentEvo project (c) NedoPC 2008-2011
  4. //
  5. // vertical blank, sync and window. H is period of horizontal sync;
  6. // from the last non-blanked line:
  7. // 3H is pre-blank,
  8. // 2.xxH is vertical sync (slightly more than 2H, all hsync edges preserved)
  9. // vblank is total of 25H
  10.  
  11. module video_sync_v(
  12.  
  13.         input  wire        clk,
  14.  
  15.         input  wire        hsync_start, // synchronizing signal
  16.         input  wire        line_start,  // to end vsync some time after hsync has ended
  17.  
  18.         input  wire        hint_start,
  19.  
  20.  
  21.  
  22.         // atm video mode input
  23.         input  wire        mode_atm_n_pent,
  24.  
  25.  
  26.  
  27.         output reg         vblank,
  28.         output reg         vsync,
  29.  
  30.         output reg         int_start, // one-shot positive pulse marking beginning of INT for Z80
  31.  
  32.         output reg         vpix // vertical picture marker: active when there is line with pixels in it, not just a border. changes with hsync edge
  33. );
  34.  
  35.  
  36.  
  37.  
  38.  
  39.         localparam VBLNK_BEG = 9'd00;
  40.         localparam VSYNC_BEG = 9'd08;
  41.         localparam VSYNC_END = 9'd11;
  42.         localparam VBLNK_END = 9'd32;
  43.  
  44.         localparam INT_BEG = 9'd0;
  45.  
  46.         // pentagon (x192)
  47.         localparam VPIX_BEG_PENT = 9'd080;//9'd064;
  48.         localparam VPIX_END_PENT = 9'd272;//9'd256;
  49.  
  50.         // ATM (x200)
  51.         localparam VPIX_BEG_ATM = 9'd076;//9'd060;
  52.         localparam VPIX_END_ATM = 9'd276;//9'd260;
  53.  
  54.         localparam VPERIOD = 9'd320; // pentagono foreva!
  55.  
  56.  
  57.         reg [8:0] vcount;
  58.  
  59.  
  60.  
  61.  
  62.         initial
  63.         begin
  64.                 vcount = 9'd0;
  65.                 vsync = 1'b0;
  66.                 vblank = 1'b0;
  67.                 vpix = 1'b0;
  68.                 int_start = 1'b0;
  69.         end
  70.  
  71.         always @(posedge clk) if( hsync_start )
  72.         begin
  73.                 if( vcount==(VPERIOD-9'd1) )
  74.                         vcount <= 9'd0;
  75.                 else
  76.                         vcount <= vcount + 9'd1;
  77.         end
  78.  
  79.  
  80.  
  81.         always @(posedge clk) if( hsync_start )
  82.         begin
  83.                 if( vcount==VBLNK_BEG )
  84.                         vblank <= 1'b1;
  85.                 else if( vcount==VBLNK_END )
  86.                         vblank <= 1'b0;
  87.         end
  88.  
  89.  
  90.         always @(posedge clk)
  91.         begin
  92.                 if( (vcount==VSYNC_BEG) && hsync_start )
  93.                         vsync <= 1'b1;
  94.                 else if( (vcount==VSYNC_END) && line_start  )
  95.                         vsync <= 1'b0;
  96.         end
  97.  
  98.  
  99.         always @(posedge clk)
  100.         begin
  101.                 if( (vcount==INT_BEG) && hint_start )
  102.                         int_start <= 1'b1;
  103.                 else
  104.                         int_start <= 1'b0;
  105.         end
  106.  
  107.  
  108.  
  109.         always @(posedge clk) if( hsync_start )
  110.         begin
  111.                 if( vcount==(mode_atm_n_pent ? VPIX_BEG_ATM : VPIX_BEG_PENT) )
  112.                         vpix <= 1'b1;
  113.                 else if( vcount==(mode_atm_n_pent ? VPIX_END_ATM : VPIX_END_PENT) )
  114.                         vpix <= 1'b0;
  115.         end
  116.  
  117.  
  118. endmodule
  119.  
  120.