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  1. module main(
  2.  
  3.  // clocks
  4.  input fclk,
  5.  output clkz_out,
  6.  input clkz_in,
  7.  
  8.  // z80
  9.  input iorq_n,
  10.  input mreq_n,
  11.  input rd_n,
  12.  input wr_n,
  13.  input m1_n,
  14.  input rfsh_n,
  15.  input int_n,
  16.  input nmi_n,
  17.  input wait_n,
  18.  output res,
  19.  
  20.  inout [7:0] d,
  21.  output [15:0] a,
  22.  
  23.  // zxbus and related
  24.  output csrom,
  25.  output romoe_n,
  26.  output romwe_n,
  27.  
  28.  output rompg0_n,
  29.  output dos_n, // aka rompg1
  30.  output rompg2,
  31.  output rompg3,
  32.  output rompg4,
  33.  
  34.  input iorqge1,
  35.  input iorqge2,
  36.  output iorq1_n,
  37.  output iorq2_n,
  38.  
  39.  // DRAM
  40.  input [15:0] rd,
  41.  input [9:0] ra,
  42.  output rwe_n,
  43.  output rucas_n,
  44.  output rlcas_n,
  45.  output rras0_n,
  46.  output rras1_n,
  47.  
  48.  // video
  49.  output reg [1:0] vred,
  50.  output reg [1:0] vgrn,
  51.  output reg [1:0] vblu,
  52.  
  53.  output vhsync,
  54.  output vvsync,
  55.  output vcsync,
  56.  
  57.  // AY control and audio/tape
  58.  input ay_clk,
  59.  output ay_bdir,
  60.  output ay_bc1,
  61.  
  62.  output beep,
  63.  
  64.  // IDE
  65.  input [2:0] ide_a,
  66.  input [15:0] ide_d,
  67.  
  68.  output ide_dir,
  69.  
  70.  input ide_rdy,
  71.  
  72.  output ide_cs0_n,
  73.  output ide_cs1_n,
  74.  output ide_rs_n,
  75.  output ide_rd_n,
  76.  output ide_wr_n,
  77.  
  78.  // VG93 and diskdrive
  79.  input vg_clk,
  80.  
  81.  output vg_cs_n,
  82.  output vg_res_n,
  83.  
  84.  input vg_hrdy,
  85.  input vg_rclk,
  86.  input vg_rawr,
  87.  input [1:0] vg_a, // disk drive selection
  88.  input vg_wrd,
  89.  input vg_side,
  90.  
  91.  input step,
  92.  input vg_sl,
  93.  input vg_sr,
  94.  input vg_tr43,
  95.  input rdat_b_n,
  96.  input vg_wf_de,
  97.  input vg_drq,
  98.  input vg_irq,
  99.  input vg_wd,
  100.  
  101.  // serial links (atmega-fpga, sdcard)
  102.  output sdcs_n,
  103.  output sddo,
  104.  output sdclk,
  105.  input sddi,
  106.  
  107.  input spics_n,
  108.  input spick,
  109.  input spido,
  110.  output spidi,
  111.  input spiint_n
  112. );
  113.  
  114. //--Dummy----------------------------------------------------------------------
  115.  
  116.  assign iorq1_n = 1'b1;
  117.  assign iorq2_n = 1'b1;
  118.  
  119.  assign res= 1'b1;
  120.  
  121.  assign rwe_n   = 1'b1;
  122.  assign rucas_n = 1'b1;
  123.  assign rlcas_n = 1'b1;
  124.  assign rras0_n = 1'b1;
  125.  assign rras1_n = 1'b1;
  126.  
  127.  assign ay_bdir = 1'b0;
  128.  assign ay_bc1  = 1'b0;
  129.  
  130.  assign vg_cs_n  = 1'b1;
  131.  assign vg_res_n = 1'b0;
  132.  
  133.  assign ide_dir=1'b1;
  134.  assign ide_rs_n = 1'b0;
  135.  assign ide_cs0_n = 1'b1;
  136.  assign ide_cs1_n = 1'b1;
  137.  assign ide_rd_n = 1'b1;
  138.  assign ide_wr_n = 1'b1;
  139.  
  140.  assign a[15:14] = 2'b00;
  141.  
  142. //-----------------------------------------------------------------------------
  143.  
  144.  reg [2:0] main_osc;
  145.  
  146.  always @(posedge fclk)
  147.   main_osc <= main_osc + 3'h1;
  148.  
  149.  assign clkz_out = main_osc[2]; // 3.5 MHz
  150.  assign beep = spiint_n;
  151.  
  152. //--Video----------------------------------------------------------------------
  153.  
  154.  localparam HBLNK_BEG  = 9'd384;
  155.  localparam CSYNC_CUT  = 9'd415;
  156. //localparam CSYNC_CUT2 = 9'd382;
  157.  localparam HSYNC_BEG  = 9'd0;
  158.  localparam HSYNC_END  = 9'd33;
  159.  localparam HSYNC_END2 = 9'd53;
  160.  localparam HBLNK_END  = 9'd128;
  161.  localparam HMAX       = 9'd447;
  162.  localparam VBLNK_BEG  = 10'd512; // 256
  163.  localparam VSYNC_BEG  = 10'd0;   // 0
  164.  localparam VSYNC_END  = 10'd4;   // 2
  165.  localparam VBLNK_END  = 10'd128; // 64
  166.  localparam VMAX       = 10'd623; // 311
  167.  
  168.  reg [8:0] hcount;
  169.  reg [9:0] vcount;
  170.  reg [5:0] hcharcount;
  171.  reg [2:0] vcharline;
  172.  reg [6:0] voffset;
  173.  reg hsync, hblank, vsync, vblank, csync;
  174.  wire [9:0] video_addr;
  175.  wire [6:0] charcode;
  176.  wire [7:0] charpix;
  177.  wire pixel;
  178.  wire [5:0] fcolor;
  179.  wire [5:0] bcolor;
  180.  wire [5:0] color;
  181.  
  182.  always @(posedge fclk)
  183.   begin
  184.    //
  185.    if ( {(main_osc[1]&scr_tv_mode),main_osc[0]}==2'h0 )
  186.     begin
  187.  
  188.      if ( hcount[2:0]==3'h0 )
  189.       begin
  190.        if ( hblank )
  191.         hcharcount <= 6'h00;
  192.        else
  193.         hcharcount <= hcharcount + 6'h01;
  194.       end
  195.  
  196.      if ( hcount==HMAX )
  197.       hcount <= 9'd0;
  198.      else
  199.       hcount <= hcount + 9'd1;
  200.  
  201.      if ( hcount==HBLNK_BEG )
  202.       hblank <= 1'b1;
  203.      else if ( hcount==HBLNK_END )
  204.       hblank <= 1'b0;
  205.  
  206.      if ( hcount==HSYNC_BEG )
  207.       begin
  208.        hsync <= 1'b1;
  209.        if ( vc0 )
  210.         csync <= 1'b1;
  211.       end
  212.  
  213.      if ( (~scr_tv_mode) && (hcount==HSYNC_END2) )
  214.       begin
  215.        hsync <= 1'b0;
  216.        if ( !vsync )
  217.         csync <= 1'b0;
  218.       end
  219.  
  220.      if ( scr_tv_mode && (hcount==HSYNC_END) )
  221.       begin
  222.        hsync <= 1'b0;
  223.        if ( !vsync )
  224.         csync <= 1'b0;
  225.       end
  226.  
  227.      if ( (~vc0) && (hcount==HBLNK_BEG) ) // localparam CSYNC_CUT2 = 9'd382;
  228.       csync <= 1'b0;
  229.  
  230.      if ( scr_tv_mode && (hcount==CSYNC_CUT) )
  231.       csync <= 1'b0;
  232.  
  233.      vgrn[1] <= color[5];
  234.      vgrn[0] <= color[4];
  235.      vred[1] <= color[3];
  236.      vred[0] <= color[2];
  237.      vblu[1] <= color[1];
  238.      vblu[0] <= color[0];
  239.  
  240.     end
  241.    //
  242.    if ( (main_osc[1:0]==2'h3) && (hcount==HSYNC_BEG) )
  243.     begin
  244.  
  245.      if ( vblank )
  246.       begin
  247.        voffset <= 7'd0;
  248.        vcharline <= 3'h0;
  249.       end
  250.      else
  251.       begin
  252.        if ( (vcharline==3'h7) && vc0 )
  253.         voffset <= voffset + 7'd4;  //  32 / 8 = 4
  254.        vcharline <= vcharline + {2'b00,vc0};
  255.       end
  256.  
  257.      if ( {vcount[9:1],vc0}==VMAX )
  258.       vcount <= 10'd0;
  259.      else
  260.       vcount <= {vcount[9:1],vc0} + 10'd1;
  261.  
  262.      if ( vcount==VBLNK_BEG )
  263.       vblank <= 1'b1;
  264.      else if ( vcount==VBLNK_END )
  265.       vblank <= 1'b0;
  266.  
  267.      if ( vcount==VSYNC_BEG )
  268.       vsync <= 1'b1;
  269.      else if ( vcount==VSYNC_END )
  270.       vsync <= 1'b0;
  271.  
  272.     end
  273.    //
  274.   end
  275.  
  276.  assign vc0 = vcount[0] | scr_tv_mode;
  277.  assign video_addr = { voffset[6:0], 3'h0 } + { 4'h0, hcharcount[5:0] };
  278.  lpm_ram_dp0 scr_mem  ( .data(scr_char), .rdaddress(video_addr), .wraddress(scr_addr), .wren(scr_wren_c), .q(charcode) );
  279.  lpm_rom0 chargen ( .address({ charcode, vcharline[2:0] }), .q(charpix) );
  280.  
  281.  assign fcolor = 6'b111111;
  282.  assign bcolor = 6'b000001;
  283.  assign pixel = charpix[~(hcount[2:0]-3'h1)];
  284.  assign color = (hblank | vblank) ? 6'h00 : ( pixel ? fcolor : bcolor ) ;
  285.  
  286.  assign vhsync = hsync;
  287.  assign vvsync = vsync;
  288.  assign vcsync = ~csync;
  289.  
  290. //--AVRSPI--FlashROM-----------------------------------------------------------
  291.  
  292.  localparam SD_CS0        = 8'h57;
  293.  localparam SD_CS1        = 8'h5f;
  294.  localparam FLASH_LOADDR  = 8'hf0;
  295.  localparam FLASH_MIDADDR = 8'hf1;
  296.  localparam FLASH_HIADDR  = 8'hf2;
  297.  localparam FLASH_DATA    = 8'hf3;
  298.  localparam FLASH_CTRL    = 8'hf4;
  299.  localparam SCR_LOADDR    = 8'h40;
  300.  localparam SCR_HIADDR    = 8'h41;
  301.  localparam SCR_CHAR      = 8'h44;
  302.  localparam SCR_MODE      = 8'h4e;
  303.  
  304.  reg [7:0] number;
  305.  reg [7:0] indata;
  306.  reg [7:0] outdata;
  307.  reg [2:0] bitptr;
  308.  reg [1:0] spick_resync;
  309.  reg [1:0] spicsn_resync;
  310.  reg [18:0] flash_addr;
  311.  reg flash_cs;
  312.  reg flash_oe;
  313.  reg flash_we;
  314.  reg [7:0] flash_data_out;
  315.  reg [9:0] scr_addr;
  316.  reg [6:0] scr_char;
  317.  reg scr_wren_c;
  318.  reg scr_tv_mode;
  319.  wire spicsn_rising;
  320.  wire spicsn_falling;
  321.  wire sd_selected;
  322.  
  323.  always @(posedge spick)
  324.   begin
  325.    if ( spics_n )
  326.     number <= { number[6:0], spido };
  327.    else
  328.     indata <= { indata[6:0], spido };
  329.   end
  330.  
  331.  always @(negedge spick or posedge spics_n)
  332.   begin
  333.    if ( spics_n )
  334.     bitptr <= 3'b111;
  335.    else
  336.     bitptr <= bitptr - 3'b001;
  337.   end
  338.  
  339.  always @(posedge fclk)
  340.   begin
  341.  
  342.    spicsn_resync <= { spicsn_resync[0], spics_n };
  343.  
  344.    if ( spicsn_rising )
  345.     case ( number )
  346.      FLASH_LOADDR:  flash_addr[7:0] <= indata;
  347.      FLASH_MIDADDR: flash_addr[15:8] <= indata;
  348.      FLASH_HIADDR:  flash_addr[18:16] <= indata[2:0];
  349.      FLASH_DATA:    flash_data_out <= indata;
  350.      FLASH_CTRL:    begin
  351.                      flash_cs <= indata[0];
  352.                      flash_oe <= indata[1];
  353.                      flash_we <= indata[2];
  354.                     end
  355.      SCR_LOADDR:    scr_addr[7:0] <= indata;
  356.      SCR_HIADDR:    scr_addr[9:8] <= indata[1:0];
  357.      SCR_CHAR:      begin
  358.                      scr_char <= indata[6:0];
  359.                      scr_wren_c <= 1'b1;
  360.                     end
  361.      SCR_MODE:      scr_tv_mode <= ~indata[0];
  362.     endcase
  363.  
  364.    if ( spicsn_falling )
  365.     begin
  366.      scr_wren_c <= 1'b0;
  367.      if ( number==SCR_CHAR )
  368.       scr_addr <= scr_addr + 10'd1;
  369.      if ( number==FLASH_DATA )
  370.       outdata <= d;
  371.      else
  372.       outdata <= 8'hff;
  373.     end
  374.  
  375.   end
  376.  
  377.  assign spicsn_rising  = (spicsn_resync==2'b01);
  378.  assign spicsn_falling = (spicsn_resync==2'b10);
  379.  
  380.  assign sd_selected = ( ( (number==SD_CS0) || (number==SD_CS1) ) && (~spics_n) );
  381.  assign spidi = sd_selected ? sddi : outdata[bitptr];
  382.  assign sddo  = sd_selected ? spido : 1'b1;
  383.  assign sdclk = sd_selected ? spick : 1'b0;
  384.  assign sdcs_n = !( (number==SD_CS0) && (~spics_n) );
  385.  
  386.  assign a[13:0]  =  flash_addr[13:0];
  387.  assign rompg0_n = ~flash_addr[14];
  388.  assign { rompg4, rompg3, rompg2, dos_n } = flash_addr[18:15];
  389.  assign csrom   =  flash_cs;
  390.  assign romoe_n = ~flash_oe;
  391.  assign romwe_n = ~flash_we;
  392.  assign d = flash_oe ? 8'bZZZZZZZZ : flash_data_out;
  393.  
  394. //-----------------------------------------------------------------------------
  395.  
  396. endmodule
  397.